AT90PWM81-16SF Atmel, AT90PWM81-16SF Datasheet - Page 69
AT90PWM81-16SF
Manufacturer Part Number
AT90PWM81-16SF
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM81-16MN.pdf
(325 pages)
Specifications of AT90PWM81-16SF
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90PWM81-16SF
Manufacturer:
Atmel
Quantity:
2 428
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7734P–AVR–08/10
Figure 9-3.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is
closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded
region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is
clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows
t
period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in
9-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the
delay t
Figure 9-4.
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port
pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back
pd,max
and t
pd
through the synchronizer is 1 system clock period.
pd,min
INSTRUCTIONS
INSTRUCTIONS
Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK
Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
SYNC LATCH
SYNC LATCH
, a single signal transition on the pin will be delayed between ½ and 1½ system clock
PINxn
PINxn
r17
r16
r17
out PORTx, r16
XXX
t
pd, max
0x00
0x00
XXX
nop
t
pd
t
0xFF
pd, min
in r17, PINx
in r17, PINx
AT90PWM81
0xFF
0xFF
Figure
69
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