AT90PWM81-16SF Atmel, AT90PWM81-16SF Datasheet - Page 181
AT90PWM81-16SF
Manufacturer Part Number
AT90PWM81-16SF
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM81-16MN.pdf
(325 pages)
Specifications of AT90PWM81-16SF
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number:
AT90PWM81-16SF
Manufacturer:
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7734P–AVR–08/10
The interconnection between Master and Slave CPUs with SPI is shown in
sists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication
cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to
be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK
line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI,
line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Mas-
ter will synchronize the Slave by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be han-
dled by user software before communication can start. When this is done, writing a byte to the SPI Data
Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting
one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI Interrupt
Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift
the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line.
The last incoming byte will be kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS
pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the
data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one
byte has been completely shifted, the end of transmission flag, SPIF is set. If the SPI Interrupt Enable bit,
SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to
be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer
Register for later use.
Figure 14-2.
The system is single buffered in the transmit direction and double buffered in the receive direction. This
means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle
is completed. When receiving data, however, a received character must be read from the SPI Data Regis-
ter before the next character has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct
sampling of the clock signal, the frequency of the SPI clock should never exceed f
SPI Master-slave Interconnection
Figure
AT90PWM81
clkio
14-2. The system con-
/4.
SHIFT
ENABLE
181
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