AT90PWM81-16SF Atmel, AT90PWM81-16SF Datasheet - Page 261
AT90PWM81-16SF
Manufacturer Part Number
AT90PWM81-16SF
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM81-16MN.pdf
(325 pages)
Specifications of AT90PWM81-16SF
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90PWM81-16SF
Manufacturer:
Atmel
Quantity:
2 428
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21.7.14
21.8
21.8.1
7734P–AVR–08/10
Serial Downloading
Reading the Calibration Byte
Serial Programming Algorithm
The algorithm for reading the Calibration byte is as follows (refer to
256
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is
pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET
is set low, the Programming Enable instruction needs to be executed first before program/erase operations
can be executed. NOTE, in
all parts use the SPI pins dedicated for the internal SPI interface.
Figure 21-7.
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation
(in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip
Erase operation turns the content of every memory location in both the Program and EEPROM arrays into
0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the
serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the AT90PWM81, data is clocked on the rising edge of SCK.
1.
2.
3.
4.
for details on Command and Address loading):
A: Load Command “0000 1000”.
B: Load Address Low Byte, 0x00.
Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
Set OE to “1”.
2.
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1
2. V
pin.
CC
Serial Programming and Verify
- 0.3V < AVCC < V
Table 21-13 on page
MOSI_A
MISO_A
SCK_A
ck
ck
CC
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
XTAL1
RESET
GND
(1)
254, the pin mapping for SPI programming is listed. Not
AVCC
VCC
+1.8 - 5.5V
+1.8 - 5.5V
“Programming the Flash” on page
ck
ck
(2)
>= 12 MHz
>= 12 MHz
AT90PWM81
261
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