AT90PWM81-16SF Atmel, AT90PWM81-16SF Datasheet - Page 41

• Manufacturer Part Number: AT90PWM81-16SF
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SF

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5.4
5.5.5
7734P–AVR–08/10
MCU Control Register – MCUCR
CLKCSR – Clock Control & Status Register
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is started as PLL
reference clock. If PLL is selected as a system clock source the value for this bit is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable CLK
PSC. The time to lock is specified in
Notes:
• Bit 2– CKRC81: Frequency Selection of the calibrated 8/1 MHz RC Oscillator
Thanks to CKRC81 in MCUCR Sfr, the typical frequency of the calibrated RC oscillator is changed.
Note:
Note:
Note:
• Bit 7 – CLKCCE: Clock Control Change Enable
The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The CLKCCE bit is
only updated when the other bits in CLKCSR are simultaneously written to zero. CLKCCE is cleared by
hardware four cycles after it is written or when the CLKCSR bits are written. Rewriting the CLKCCE bit
within this time-out period does neither extend the time-out period, nor clear the CLKCCE bit.
• Bits 6:5 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM81 and will always read as zero.
• Bits 4 – CLKRDY: Clock Ready Flag
This flag is the output of the ‘Clock Availability’ logic.
This flag is reset once the ‘Request for Clock Availability’ command is entered.
It is set when ‘Clock Availability’ logic confirms that the (selected) clock is running and is stable. The
delay from the request and the flag setting is not fixed, it depends on the clock start-up time, the clock
frequency and, of course, if the clock is alive. The user’s has itself to do the difference between
‘no_clock_signal’ and ‘clock_signal_not_yet_available’.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
– When the CKRC81 bit is written to zero, the RC oscillator frequency is 8 MHz.
– When the CKRC81 bit is written to one, the RC oscillator frequency is 1 MHz.
1. V alue is Initialized with the fuse CKSEL2
2. Value is initialized with fuses CKSEL3..0 (1 when CKSEL3..0= 0110, 0 in all other cases)
This be only can be changed only when the RC oscillator is enabled.
When the RC oscillator is used as the PLL source, CKRC81 must not be written to 1.
If the RC oscillator is disabled, this bit is cleared by hardware
CLKCCE
7
–
R
0
R/W
7
0
6
–
R
0
R
6
–
0
5
–
R
0
Table 5-9 on page
R
5
–
0
CLKRDY
4
PUD
R/W
0
R
4
0
34.
3
RSTDIS
R/W
0/1
CLKC3
R/W
(1)
3
0
2
CKRC81
R/W
0
CLKC2
R/W
2
0
1
IVSEL
R/W
0
CLKC1
R/W
AT90PWM81
1
0
0
IVCE
R/W
0
CLKC0
R/W
0
0
CLKCSR
MCUCR
PLL
for
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