AT90PWM81-16SF Atmel, AT90PWM81-16SF Datasheet - Page 33
AT90PWM81-16SF
Manufacturer Part Number
AT90PWM81-16SF
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM81-16MN.pdf
(325 pages)
Specifications of AT90PWM81-16SF
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90PWM81-16SF
Manufacturer:
Atmel
Quantity:
2 428
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5.2.5
5.2.6
7734P–AVR–08/10
External Clock
PLL
To drive the device from this external clock source, CLKI should be driven as shown in
the device on an external clock, the CKSEL Fuses or CSEL field must be programmed as shown in
5-1 on page
Figure 5-3.
When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT field as
shown in
Table 5-8.
Notes:
Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock fre-
quency while still ensuring stable operation. Refer to
To generate high frequency and accurate PWM waveforms, the ‘PSC’s need high frequency clock input.
This clock is generated by a PLL. To keep all PWM accuracy, the frequency factor of PLL must be con-
figured by software..
The internal PLL in AT90PWM81 generates a clock frequency multiplied from nominally 8 MHz input.
The source of the 8 MHz PLL input clock can be selected from three possible sources (See the
on page
•
•
•
The internal PLL is enabled only when the PLLE bit in the register PLLCSR is set. The bit PLOCK from
the register PLLCSR is set when PLL is locked.
When selected as clock source by fuse, the PLL multiplication factor is initialized at the value of 6, com-
patible with a 3V supply.
CSUT1..0
SUT1..0
Internal RC Oscillator
Crystal oscillator
External clock
00
01
10
11
34) :
1. Flash Fuse bits.
2. CLKSELR register bits.
Table
(1)
28.
(2)
5-8.
External Clock Drive Configuration
Start-up Times for the External Clock Selection
Start-up Time from
Power-down
6 CK
6 CK
6 CK
External
Signal
Clock
Additional Delay from Reset
14CK + 64 ms
“System Clock Prescaler” on page 38
14CK + 4 ms
14CK
Reserved
(XTAL1)
CLKI
GND
AT90PWM81
BOD enabled
Fast rising power
Slowly rising power
Recommended Usage
Figure
for details.
5-3. To run
Figure 5-4
Table
33
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