ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 12

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.7
5.8
12
Instruction Execution Timing
Reset and Interrupt Handling
Atmel ATtiny24/44/84 [Preliminary]
This section describes the general access timing concepts for instruction execution. The
Atmel
clock source for the chip. No internal clock division is used.
Figure 5-4 on page 12
enabled by the Harvard architecture and the fast access register file concept. This is the basic
pipelining concept to obtain up to 1MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 5-4.
Figure 5-5 on page 12
cycle an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 5-5.
The Atmel AVR provides several different interrupt sources. These interrupts and the separate
reset vector each have a separate program vector in the program memory space. All interrupts
are assigned individual enable bits which must be written with a logical one together with the
global interrupt enable bit in the status register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address, the higher the
priority level. RESET has the highest priority, and next is INT0, the external interrupt request
0.
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
®
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
AVR
Result Write Back
®
CPU is driven by the CPU clock clk
The Parallel Instruction Fetches and Instruction Executions
Single-cycle ALU Operation
clk
clk
CPU
CPU
shows the internal timing concept for the Register File. In a single clock
shows the parallel instruction fetches and instruction executions
T1
T1
CPU
T2
T2
, directly generated from the selected
“Interrupts” on page
T3
T3
49. The list also
7701D–AVR–09/10
T4
T4