ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 76

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.6.1
13.7
13.7.1
13.7.2
76
Modes of Operation
Atmel ATtiny24/44/84 [Preliminary]
Compare Output Mode and Waveform Generation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
The design of the output compare pin logic allows initialization of the OC0x state before the
output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of
operation, see
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action
on the OC0x Register is to be performed on the next Compare Match. For compare output
actions in the non-PWM modes refer to
Table 13-3 on page
A change of the COM0x1:0 bit states will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the 0x strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare
Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For
non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or tog-
gled at a Compare Match (See
For detailed timing information refer to
ure 13-10 on page 82
page
The simplest mode of operation is the normal mode (WGM02:0 = 0). In this mode, the count-
ing direction is always up (incrementing), and no counter clear is performed. The counter
simply overruns when it passes its maximum 8-bit value (top = 0xFF) and then restarts from
the bottom (0x00). In normal operation the timer/counter overflow flag (TOV0) will be set on
the same timer clock cycle on which the TCNT0 becomes zero. The TOV0 flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the
timer overflow interrupt that automatically clears the TOV0 flag, the timer resolution can be
increased by software. There are no special cases to consider in the normal mode. A new
counter value can be written anytime.
The output compare unit can be used to generate interrupts at some given time. Using the out-
put compare to generate waveforms in normal mode is not recommended, since this will
occupy too much CPU time.
In clear timer on compare, or CTC, mode (WGM02:0 = 2), the OCR0A register is used to
manipulate the counter resolution. In CTC mode, the counter is cleared to zero when the
counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the coun-
ter, hence also its resolution. This mode allows greater control of the compare match output
frequency. It also simplifies the operation of counting external events.
81.
“Register Description” on page 83
83, and for phase correct PWM refer to
and
Figure 13-11 on page 82
“Modes of Operation” on page
Figure 13-8 on page
Table 13-2 on page
in
“Timer/Counter Timing Diagrams” on
Table 13-4 on page
81,
83. For fast PWM mode, refer to
76).
Figure 13-9 on page
7701D–AVR–09/10
84.
81,
Fig-