ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 45

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.10
9.10.1
9.10.2
7701D–AVR–09/10
Register Description
MCUSR – MCU Status Register
WDTCSR – Watchdog Timer Control and Status Register
The MCU Status Register provides information on which reset source caused an MCU Reset.
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing
a logical zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing
a logical zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logical zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the
flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con-
figured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit
in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable
When this bit is written to logical one, WDE is cleared, and the I-bit in the status register is set,
the watchdog time-out interrupt is enabled. In this mode the corresponding interrupt is exe-
cuted instead of a reset if a time-out in the watchdog timer occurs.
Bit
0x34 (0x54)
Read/Write
Initial Value
Bit
0x21 (0x41)
Read/Write
Initial Value
WDIF
R/W
7
0
R
7
–
0
WDIE
R/W
6
0
R
6
–
0
Atmel ATtiny24/44/84 [Preliminary]
WDP3
R/W
5
0
R
5
–
0
WDCE
R/W
4
0
R
4
–
0
WDE
WDRF
R/W
R/W
X
3
3
WDP2
R/W
BORF
See Bit Description
R/W
2
0
2
WDP1
R/W
EXTRF
1
0
R/W
1
WDP0
R/W
PORF
0
0
R/W
0
WDTCSR
MCUSR
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