ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 159

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4.1
20.4.2
20.4.3
7701D–AVR–09/10
EEPROM Write Prevents Writing to SPMCSR
Reading the Lock and Fuse Bits from Software
Preventing Flash Corruption
Note that an EEPROM write operation will block all software programming to flash. Reading
the fuses and lock bits from software will also be prevented during the EEPROM write opera-
tion. It is recommended that the user check the status bit (EEPE) in the EECR register and
verify that the bit is cleared before writing to SPMCSR.
It is possible to read both the lock and fuse bits from software. To read the lock bits, load the
Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruc-
tion is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR,
the value of the lock bits will be loaded in the destination register. The RFLB and SPMEN bits
will auto-clear upon completion of reading the lock bits, or if no LPM instruction is executed
within three CPU cycles, or if no SPM instruction is executed within four CPU cycles. When
RFLB and SPMEN are cleared, LPM will work as described in the instruction set summary.
The algorithm for reading the fuse low byte (FLB) is similar to the one described above for
reading the lock bits. To read the fuse low byte, load the Z-pointer with 0x0000 and set the
RFLB and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the RFLB and SPMEN bits are set in the SPMCSR, the value of the fuse low byte will be
loaded in the destination register as shown below. See
description and mapping of the fuse low byte.
Similarly, when reading the fuse high byte (FHB), load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the RFLB and SPMEN bits are set in the
SPMCSR, the value of the fuse high byte will be loaded in the destination register as shown
below. See
Lock and fuse bits that are programmed will be read as zero. Lock and fuse bits that are
unprogrammed, will be read as one.
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for
board-level systems using flash, and the same design solutions should be applied.
Flash program corruption can occur for two reasons when the voltage is too low. First, a regu-
lar write sequence to the flash requires a minimum voltage to operate correctly. Secondly, the
CPU itself can execute instructions incorrectly if the supply voltage is too low.
Bit
Rd
Bit
Rd
Bit
Rd
Table 21-4 on page 163
FLB7
FHB7
7
7
7
–
CC
FLB6
FHB6
, the Flash program can be corrupted because the supply voltage is
6
6
6
–
Atmel ATtiny24/44/84 [Preliminary]
FLB5
FHB5
5
5
5
–
for detailed description and mapping of the fuse high byte.
FLB4
FHB4
4
–
4
4
FHB3
FLB3
3
–
3
3
Table 21-5 on page 164
FHB2
FLB2
2
–
2
2
FHB1
FLB1
LB2
1
1
1
FHB0
FLB0
LB1
0
0
0
for a detailed
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