ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 43

MCU AVR 2K FLASH 15MHZ 14-SOIC

ATTINY24-15SSZ

Manufacturer Part Number
ATTINY24-15SSZ
Description
MCU AVR 2K FLASH 15MHZ 14-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet

Specifications of ATTINY24-15SSZ

Package / Case
14-SOIC (3.9mm Width), 14-SOL
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
SPI/UART
Total Internal Ram Size
128Byte
# I/os (max)
12
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
14
Package Type
SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY24-15SSZ
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Quantity:
20 000
9.7
9.7.1
9.8
7701D–AVR–09/10
Internal Voltage Reference
Watchdog Timer
Voltage Reference Enable Signals and Start-up Time
Figure 9-6.
The Atmel
Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
the reference is not always turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the
three conditions above to ensure that the reference is turned off before entering Power-down
mode.
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128kHz. By control-
ling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
Table 9-4 on page
The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten dif-
ferent clock cycle periods can be selected to determine the reset period. If the reset period
expires without another Watchdog Reset, the Atmel ATtiny24/44/84 resets and executes from
the Reset Vector. For timing details on the Watchdog Reset, refer to
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This
can be very helpful when using the Watchdog to wake-up from Power-down.
ACBG bit in ACSR).
CC
®
ATtiny24/44/84 features an internal bandgap reference. This reference is used for
Watchdog Reset During Operation
47. The WDR – Watchdog Reset – instruction resets the Watchdog Timer.
“System and Reset Characterizations” on page
Atmel ATtiny24/44/84 [Preliminary]
CK
Table 9-4 on page
180. To save power,
47.
43

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