ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 68

• Manufacturer Part Number: ATTINY24-15SSZ
• Description: MCU AVR 2K FLASH 15MHZ 14-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24-15SSZ

• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

68
Atmel ATtiny24/44/84 [Preliminary]
• Port B, Bit 3 – RESET/dW/PCINT11
RESET: External Reset input is active low and enabled by un-programming ("1") the RST-
DISBL fuse. Pull-up is activated and output driver and digital input are deactivated when the
pin is used as the RESET pin.
dW: When the debugWIRE enable (DWEN) fuse is programmed and lock bits are un-pro-
grammed, the debugWIRE system within the target device is activated. The RESET port pin is
configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes
the communication gateway between target and emulator.
PCINT11: Pin change interrupt source 11. The PB3 pin can serve as an external interrupt
source for pin change interrupt 1.
Table 12-8 on page 68
the overriding signals shown in
Table 12-8.
1.
2.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
RSTDISBL is 1 when the Fuse is “0” (Programmed).
DebugWIRE is enabled when DWEN fuse is programmed and lock bits are un-programmed.
PB3/
PCINT11
RSTDISBL
1
RSTDISBL
DEBUGWIRE_ENABLE
Transmit
RSTDISBL
0
0
RSTDISBL
+ PCINT11 • PCIE1
DEBUGWIRE_ENABLE
• PCINT11 • PCIE1)
dW/PCINT11 Input
Overriding Signals for Alternate Functions in PB3..PB2
RESET/dW/
(1)
(1)
(1)
(1)
+ DEBUGWIRE_ENABLE
+ DEBUGWIRE_ENABLE
+ DEBUGWIRE_ENABLE
+ DEBUGWIRE_ENABLE
and
Table 12-9 on page 69
Figure 12-5 on page
(2)
(2)
• debugWire
+ (RSTDISBL
(2)
(2)
(2)
(2)
(1)
relate the alternate functions of Port B to
61.
PB2/INT0/OC0A/CKOUT/PCINT10
CKOUT
0
CKOUT
1'b1
CKOUT + OC0A enable
CKOUT • System Clock + CKOUT • OC0A
0
PCINT10 • PCIE1 + INT0
PCINT10 • PCIE1 + INT0
INT0/PCINT10 Input
7701D–AVR–09/10