PIC18F2221-I/SS Microchip Technology, PIC18F2221-I/SS Datasheet - Page 255

• Manufacturer Part Number: PIC18F2221-I/SS
• Description: IC PIC MCU FLASH 2KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/SS

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Details

23.2
The following steps are needed to set up the HLVD
module:
1.
2.
3.
4.
5.
6.
23.3
When the module is enabled, the HLVD comparator
and voltage divider are enabled and will consume static
current. The total current consumption, when enabled,
is specified in electrical specification parameter D022B.
FIGURE 23-2:
© 2009 Microchip Technology Inc.
Disable the module by clearing the HLVDEN bit
(HLVDCON<4>).
Write the value to the HLVDL<3:0> bits that
selects the desired HLVD trip point.
Set the VDIRMAG bit to detect high voltage
(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
Enable the HLVD module by setting the
HLVDEN bit.
Clear the HLVD interrupt flag (PIR2<2>), which
may have been set from a previous interrupt.
Enable the HLVD interrupt if interrupts are
desired by setting the HLVDIE and GIE bits
(PIE<2> and INTCON<7>). An interrupt will not
be generated until the IRVST bit is set.
CASE 1:
CASE 2:
Enable HLVD
Enable HLVD
HLVD Setup
Current Consumption
HLVDIF
HLVDIF
IRVST
IRVST
V
V
DD
DD
LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)
PIC18F2221/2321/4221/4321 FAMILY
Internal Reference is stable
Internal Reference is stable
T
T
IRVST
IRVST
HLVDIF may not be set
HLVDIF cleared in software,
HLVDIF remains set since HLVD condition still exists
Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
current requirements, the HLVD circuitry may only
need to be enabled for short periods where the voltage
is checked. After doing the check, the HLVD module
may be disabled.
23.4
The internal reference voltage of the HLVD module,
specified in electrical specification parameter D420,
may be used by other internal circuitry, such as the
Programmable Brown-out Reset. If the HLVD or other
circuits using the voltage reference are disabled to
lower the device’s current consumption, the reference
voltage circuit will require time to become stable before
a low or high-voltage condition can be reliably
detected. This start-up time, T
is independent of device clock speed. It is specified in
electrical specification parameter 36.
The HLVD interrupt flag is not enabled until T
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer to
Figure 23-2 or Figure 23-3.
HLVD Start-up Time
HLVDIF cleared in software
HLVDIF cleared in software
IRVST
V
V
DS39689F-page 255
, is an interval that
LVD
LVD
IRVST
has