PIC18F2221-I/SS Microchip Technology, PIC18F2221-I/SS Datasheet - Page 397

• Manufacturer Part Number: PIC18F2221-I/SS
• Description: IC PIC MCU FLASH 2KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/SS

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Details

© 2009 Microchip Technology Inc.
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Low-Voltage Detect Operation (VDIRMAG = 0) ...... 255
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4221/4321) ................... 360
Parallel Slave Port (PSP) Read ............................... 127
Parallel Slave Port (PSP) Write ............................... 127
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 161
PWM Direction Change at Near
PWM Output ............................................................ 150
Repeated Start Condition ......................................... 200
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 227
Slave Synchronization ............................................. 173
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 172
SPI Mode (Slave Mode, CKE = 0) ........................... 174
SPI Mode (Slave Mode, CKE = 1) ........................... 174
Synchronous Reception (Master Mode, SREN) ...... 230
Synchronous Transmission ...................................... 228
Synchronous Transmission (Through TXEN) .......... 229
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 358
Transition for Entry to Idle Mode ................................ 44
Transition for Entry to SEC_RUN Mode .................... 41
Transition for Entry to Sleep Mode ............................ 43
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 44
Transition for Wake from Sleep (HSPLL) ................... 43
Transition from RC_RUN Mode to PRI_RUN Mode .. 42
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 42
2
2
2
2
2
2
2
2
2
2
2
2
C Master Mode (7 or 10-Bit Transmission) ........... 202
C Master Mode (7-Bit Reception) .......................... 203
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) .......... 188
C Slave Mode (10-Bit Reception, SEN = 1) .......... 193
C Slave Mode (10-Bit Transmission) ..................... 189
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............ 184
C Slave Mode (7-Bit Reception, SEN = 1) ............ 192
C Slave Mode (7-Bit Transmission) ....................... 186
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 204
ADMSK = 01001) ............................................. 187
ADMSK = 01011) ............................................. 185
Sequence (7 or 10-Bit Addressing Mode) ........ 194
Auto-Restart Disabled) .................................... 164
Auto-Restart Enabled) ..................................... 164
100% Duty Cycle ............................................. 161
Timer (OST), Power-up Timer (PWRT) ........... 357
V
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 271
PRI_RUN Mode (HSPLL) .................................. 41
DD
Rise > T
2
2
C Bus Data ........................................ 367
C Bus Start/Stop Bits ........................ 367
PWRT
PIC18F2221/2321/4221/4321 FAMILY
DD
DD
) ............................................ 53
) ........................................... 53
, V
DD
DD
DD
, Case 1) ....................... 52
, Case 2) ....................... 52
Rise < T
DD
,
PWRT
) ........... 52
Timing Diagrams and Specifications ............................... 354
Top-of-Stack Access .......................................................... 60
TRISE Register
TSTFSZ ........................................................................... 319
Two-Speed Start-up ................................................. 259, 271
Two-Word Instructions
TXSTA Register
V
Voltage Reference Specifications .................................... 350
W
Watchdog Timer (WDT) ........................................... 259, 269
WCOL ...................................................... 199, 200, 201, 204
WCOL Status Flag ................................... 199, 200, 201, 204
WWW Address ................................................................ 399
WWW, On-Line Support ...................................................... 8
X
XORLW ........................................................................... 319
XORWF ........................................................................... 320
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 356
EUSART Synchronous Receive Requirements ....... 369
EUSART Synchronous Transmission Requirements ....
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
External Clock Requirements .................................. 354
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Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................ 355
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
PSPMODE Bit ......................................................... 120
Example Cases ......................................................... 64
BRGH Bit ................................................................. 215
Associated Registers ............................................... 270
Control Register ....................................................... 269
During Oscillator Failure .......................................... 272
Programming Considerations .................................. 269
2
2
C Bus Data Requirements (Slave Mode) .............. 366
C Bus Start/Stop Requirements (Slave Mode) ..... 365
(All CCP Modules) ........................................... 359
369
(Master Mode, CKE = 0) .................................. 361
(Master Mode, CKE = 1) .................................. 362
(Slave Mode, CKE = 0) .................................... 363
(Slave Mode, CKE = 1) .................................... 364
Requirements .................................................. 367
(PIC18F4221/4321) ......................................... 360
Timer, Power-up Timer and
Brown-out Reset Requirements ...................... 357
Requirements .................................................. 358
2
2
C Bus Data Requirements ................ 368
C Bus Start/Stop Bits
DS39689F-page 397