PIC18F2221-I/SS Microchip Technology, PIC18F2221-I/SS Datasheet - Page 96

• Manufacturer Part Number: PIC18F2221-I/SS
• Description: IC PIC MCU FLASH 2KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/SS

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Details

PIC18F2221/2321/4221/4321 FAMILY
Example 9-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 9-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 9-1:
EXAMPLE 9-3:
Example 9-4 shows the sequence to do a 16 x 16
signed multiply. Equation 9-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
DS39689F-page 96
;
;
;
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
= (ARG1H • ARG2H • 2
ARG1L, W
ARG2L
PRODH, RES1
PRODL, RES0
ARG1H, W
ARG2H
PRODH, RES3
PRODL, RES2
ARG1L, W
ARG2H
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
ARG1H, W
ARG2L
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
(ARG1H • ARG2L • 2
(ARG1L • ARG2H • 2
(ARG1L • ARG2L)
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
16 x 16 UNSIGNED
MULTIPLY ROUTINE
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
8
8
16
) +
) +
) +
EQUATION 9-2:
EXAMPLE 9-4:
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
;
;
;
;
;
SIGN_ARG1
;
CONT_CODE
:
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVFF
MOVFF
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
= (ARG1H • ARG2H • 2
(ARG1H • ARG2L • 2
(ARG1L • ARG2H • 2
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
ARG1L, W
ARG2L
PRODH, RES1
PRODL, RES0
ARG1H, W
ARG2H
PRODH, RES3
PRODL, RES2
ARG1L, W
ARG2H
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
ARG1H, W
ARG2L
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
16 x 16 SIGNED
MULTIPLY ROUTINE
© 2009 Microchip Technology Inc.
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
; ARG1H:ARG1L neg?
; no, done
;
;
;
8
8
16
) +
) +
) +
16
16
) +
)