PIC18F2221-I/SS Microchip Technology, PIC18F2221-I/SS Datasheet - Page 38

• Manufacturer Part Number: PIC18F2221-I/SS
• Description: IC PIC MCU FLASH 2KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/SS

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Details

PIC18F2221/2321/4221/4321 FAMILY
3.8
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin in Crystal Oscillator modes) will stop
oscillating.
In
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features, regardless of the power-
managed mode (see Section 24.2 “Watchdog Timer
(WDT)”, Section 24.3 “Two-Speed Start-up” and
Section 24.4 “Fail-Safe Clock Monitor” for more
information). The INTOSC output at 8 MHz may be
used directly to clock the device or may be divided
down by the postscaler. The INTOSC output is disabled
if the clock is provided directly from the INTRC output.
The INTOSC output is also enabled for Two-Speed
Start-up at 1 MHz after a Reset.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a Real-
Time Clock. Other features may be operating that do
not require a device clock source (i.e., MSSP slave,
PSP, INTx pins and others). Peripherals that may add
significant
Section 27.2 “DC Characteristics”.
TABLE 3-3:
DS39689F-page 38
RC, INTIO1
RCIO
INTIO2
ECIO
EC
LP, XT and HS
Note:
secondary
OSC Mode
Effects of Power-Managed Modes
on the Various Clock Sources
See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.
current
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
clock
consumption
modes
Floating, external resistor pulls high
Floating, external resistor pulls high
Configured as PORTA, bit 7
Floating, driven by external clock
Floating, driven by external clock
Feedback inverter disabled at quiescent
voltage level
(SEC_RUN
are
listed
OSC1 Pin
and
in
3.9
Power-up delays are controlled by two or three timers,
so that no external Reset circuitry is required for most
applications. The delays ensure that the device is kept
in Reset until the device power supply is stable under
normal circumstances and the primary clock is operat-
ing and stable. For additional information on power-up
delays, see Section 5.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT) which
provides a fixed delay on power-up (parameter 33,
Table 27-10). It is enabled by clearing (= 0) the
PWRTEN Configuration bit (CONFIG2L<0>).
3.9.1
The second timer is the Oscillator Start-up Timer
(OST), intended to delay execution until the crystal
oscillator is stable (LP, XT and HS modes). The OST
does this by counting 1024 oscillator cycles before
allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, a third
timer delays execution for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency. At the end of these delays,
the OSTS bit (OSCCON<3>) is set.
There is a delay of interval T
Table 27-10), once execution is allowed to start, when
the controller becomes ready to execute instructions.
This delay runs concurrently with any other delays.
This may be the only delay that occurs when any of the
EC, RC or INTIO modes are used as the primary clock
source.
Power-up Delays
Configured as PORTA, bit 6
Configured as PORTA, bit 6
Feedback inverter disabled at quiescent
voltage level
At logic low (clock/4 output)
Configured as PORTA, bit 6
At logic low (clock/4 output)
DELAYS FOR POWER-UP AND
RETURN TO PRIMARY CLOCK
© 2009 Microchip Technology Inc.
OSC2 Pin
CSD
(parameter 38,