PIC18F2221-I/SS Microchip Technology, PIC18F2221-I/SS Datasheet - Page 275

• Manufacturer Part Number: PIC18F2221-I/SS
• Description: IC PIC MCU FLASH 2KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/SS

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Details

TABLE 24-3:
24.5.1
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn Configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
FIGURE 24-6:
© 2009 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
TBLPTR = 0008FFh
File Name
Results: All table writes disabled to Blockn whenever WRTn = 0.
Note 1: See Figure 24-5 for block boundaries.
Register Values
PROGRAM MEMORY
CODE PROTECTION
PC = 00BFFEh
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
PC = 003FFEh
SUMMARY OF CODE PROTECTION REGISTERS
TABLE WRITE (WRTn) DISALLOWED
PIC18F2221/2321/4221/4321 FAMILY
WRTD
Bit 7
CPD
—
—
—
—
EBTRB
WRTB
Bit 6
CPB
—
—
—
Program Memory
WRTC
Bit 5
Boot Block
—
—
—
—
—
Block 0
TBLWT*
Block 1
TBLWT*
Bit 4
A table read instruction that executes from a location
outside of that block is not allowed to read and will result
in reading ‘0’s. Figures 24-6 through 24-8 illustrate table
write and table read protection.
—
—
—
—
—
—
Note:
(1)
Configuration Bit Settings
Bit 3
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP operation or an
external programmer.
—
—
—
—
—
—
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
Bit 2
—
—
—
—
—
—
EBTR1
WRT1
Bit 1
CP1
DS39689F-page 275
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—