PIC18F2221-I/SS Microchip Technology, PIC18F2221-I/SS Datasheet - Page 87

• Manufacturer Part Number: PIC18F2221-I/SS
• Description: IC PIC MCU FLASH 2KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/SS

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Details

EXAMPLE 7-3:
7.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 7-2:
© 2009 Microchip Technology Inc.
TBLPTRU
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
PROGRAM_MEMORY
Name
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIP
OSCFIE
OSCFIF
EEPGD
Bit 7
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ COUNTER_HI
GOTO
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PIC18F2221/2321/4221/4321 FAMILY
CFGS
CMIP
CMIE
CMIF
Bit 6
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
PROGRAM_LOOP
EECON1, WREN
—
bit 21
Bit 5
—
—
—
—
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INT0IE
FREE
EEIP
EEIF
EEIE
Bit 4
; disable interrupts
; required sequence
; write 55h
; write AAh
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
WRERR
BCLIP
BCLIE
BCLIF
RBIE
Bit 3
7.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
7.6
See Section 24.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TMR0IF
HLVDIP
HLVDIF
HLVDIE
Flash Program Operation During
Code Protection
WREN
Bit 2
PROTECTION AGAINST
SPURIOUS WRITES
TMR3IP
TMR3IF
TMR3IE
INT0IF
Bit 1
WR
CCP2IP
CCP2IF
CCP2IE
RBIF
Bit 0
RD
DS39689F-page 87
Values on
Reset
page
55
55
55
55
55
57
57
58
58
58