PIC18F2221-I/SS Microchip Technology, PIC18F2221-I/SS Datasheet - Page 396

• Manufacturer Part Number: PIC18F2221-I/SS
• Description: IC PIC MCU FLASH 2KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-I/SS

• Core Size: 8-Bit
• Program Memory Size: 4KB (2K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Details

PIC18F2221/2321/4221/4321 FAMILY
Software Simulator (MPLAB SIM) .................................... 330
Special Event Trigger. See Compare (CCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ............................................ 259
Special Function Registers ................................................ 68
SPI Mode (MSSP)
SS .................................................................................... 167
SSPOV ............................................................................. 201
SSPOV Status Flag .......................................................... 201
SSPSTAT Register
Stack Full/Underflow Resets .............................................. 62
SUBFSR ........................................................................... 325
SUBFWB .......................................................................... 314
SUBLW ............................................................................ 315
SUBULNK ........................................................................ 325
SUBWF ............................................................................ 315
SUBWFB .......................................................................... 316
SWAPF ............................................................................ 316
T
Table Reads/Table Writes .................................................. 62
TBLRD ............................................................................. 317
TBLWT ............................................................................. 318
Time-out in Various Situations (table) ................................ 51
Timer0 .............................................................................. 129
Timer1 .............................................................................. 133
DS39689F-page 396
Map ............................................................................ 68
Associated Registers ............................................... 175
Bus Mode Compatibility ........................................... 175
Effects of a Reset ..................................................... 175
Enabling SPI I/O ...................................................... 171
Master Mode ............................................................ 172
Master/Slave Connection ......................................... 171
Operation ................................................................. 170
Operation in Power-Managed Modes ...................... 175
Serial Clock .............................................................. 167
Serial Data In ........................................................... 167
Serial Data Out ........................................................ 167
Slave Mode .............................................................. 173
Slave Select ............................................................. 167
Slave Select Synchronization .................................. 173
SPI Clock ................................................................. 172
Typical Connection .................................................. 171
R/W Bit ............................................................. 181, 183
Associated Registers ............................................... 131
Operation ................................................................. 130
Overflow Interrupt .................................................... 131
Prescaler .................................................................. 131
Prescaler Assignment (PSA Bit) .............................. 131
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 131
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 130
Source Edge Select (T0SE Bit) ................................ 130
Source Select (T0CS Bit) ......................................... 130
Switching Prescaler Assignment .............................. 131
16-Bit Read/Write Mode ........................................... 135
Associated Registers ............................................... 137
Interrupt .................................................................... 136
Operation ................................................................. 134
Oscillator .......................................................... 133, 135
Overflow Interrupt .................................................... 133
Resetting, Using the CCP Special Event Trigger ..... 136
Special Event Trigger (ECCP) ................................. 154
TMR1H Register ...................................................... 133
Layout Considerations ..................................... 136
Low-Power Option ........................................... 135
Timer2 .............................................................................. 139
Timer3 .............................................................................. 141
Timing Diagrams
TMR1L Register ....................................................... 133
Use as a Real-Time Clock ....................................... 136
Associated Registers ............................................... 140
Interrupt ................................................................... 140
Operation ................................................................. 139
Output ...................................................................... 140
PR2 Register ................................................... 150, 155
TMR2 to PR2 Match Interrupt .................................. 155
TMR2-to-PR2 Match Interrupt ................................. 150
16-Bit Read/Write Mode .......................................... 143
Associated Registers ............................................... 143
Operation ................................................................. 142
Oscillator .......................................................... 141, 143
Overflow Interrupt ............................................ 141, 143
Special Event Trigger (CCP) ................................... 143
TMR3H Register ...................................................... 141
TMR3L Register ....................................................... 141
A/D Conversion ........................................................ 371
Acknowledge Sequence .......................................... 204
Asynchronous Reception ......................................... 225
Asynchronous Transmission .................................... 222
Asynchronous Transmission (Back to Back) ........... 222
Automatic Baud Rate Calculation ............................ 220
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 226
Baud Rate Generator with Clock Arbitration ............ 198
BRG Overflow Sequence ......................................... 220
BRG Reset Due to SDA Arbitration During
Brown-out Reset (BOR) ........................................... 357
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Bus Collision During a Stop Condition (Case 1) ...... 209
Bus Collision During a Stop Condition (Case 2) ...... 209
Bus Collision During Start Condition
Bus Collision for Transmit and Acknowledge .......... 205
Capture/Compare/PWM (All CCP Modules) ............ 359
CLKO and I/O .......................................................... 356
Clock Synchronization ............................................. 191
Clock/Instruction Cycle .............................................. 63
EUSART Synchronous Receive (Master/Slave) ...... 369
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 361
Example SPI Master Mode (CKE = 1) ..................... 362
Example SPI Slave Mode (CKE = 0) ....................... 363
Example SPI Slave Mode (CKE = 1) ....................... 364
External Clock (All Modes Except PLL) ................... 354
Fail-Safe Clock Monitor ........................................... 273
First Start Bit Timing ................................................ 199
Full-Bridge PWM Output .......................................... 159
Half-Bridge PWM Output ......................................... 158
High/Low-Voltage Detect Characteristics ................ 351
High-Voltage Detect Operation (VDIRMAG = 1) ..... 256
I
I
2
2
C Bus Data ............................................................ 365
C Bus Start/Stop Bits ............................................ 365
Normal Operation ............................................ 226
Start Condition ................................................. 207
Condition (Case 1) ........................................... 208
Condition (Case 2) ........................................... 208
(SCL = 0) ......................................................... 207
(SDA Only) ...................................................... 206
(Master/Slave) ................................................. 369
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