AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 151
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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12.3
Figure 12-1. PM Block Diagram
12.4
Table 12-1.
12.5
12.5.1
12.5.2
12.5.3
32099F–11/2010
Name
RESET_N
Block Diagram
I/O Lines Description
Product Dependencies
Interrupt
Clock Implementation
Power Considerations
External Reset Pad
I/O Lines Description
Power-On
The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using
the PM interrupt requires the interrupt controller to be programmed first.
In AT32UC3L, the HSB shares the source clock with the CPU. This means that writing to the
HSBSEL register has no effect. This register will always read the same value as CPUSEL.
The clock for the PM bus interface (CLK_PM) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager, whoever if disabled it can only be
re-enabled by a reset.
The Shutdown mode is only available for the “3.3V supply mode, with 1.8V regulated I/O
lines“ power configuration.
Detector
Main Clock Sources
Description
Reset
Reset Sources
Interrupts
Clock Generator
Reset Controller
Sleep Controller
Type
Input
Synchronous
AT32UC3L016/32/64
Synchronous
CPU, HSB,
Instruction
Active Level
Low
Resets
clocks
Sleep
PBx
151
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