AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 484

• Manufacturer Part Number: AT32UC3L064-AUT
• Description: MCU AVR32 64KB FLASH 48TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L064-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI/TWI/USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.9.1
Name:
Access Type:
Offset:
Reset Value:
• STOP: Stop the current transfer
• SWRST: Software Reset
• SMDIS: SMBus Disable
• SMEN: SMBus Enable
• MDIS: Master Disable
• MEN: Master enable
32099F–11/2010
SWRST
31
23
15
7
-
-
-
Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle. If there are
additional pending transfers, they will have to be explicitly restarted by software after the STOP condition has been successfully
sent.
Writing a zero to this bit has no effect.
If the TWIM master interface is enabled, writing a one to this bit resets the TWIM. All transfers are halted immediately, possibly
violating the bus semantics.
If the TWIM master interface is not enabled, it must first be enabled before writing a one to this bit.
Writing a zero to this bit has no effect.
Writing a one to this bit disables SMBus mode.
Writing a zero to this bit has no effect.
Writing a one to this bit enables SMBus mode.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the master interface.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the master interface.
Writing a zero to this bit has no effect.
Control Register (CR)
30
22
14
6
-
-
-
-
CR
Write-only
0x00
0x00000000
SMDIS
29
21
13
5
-
-
-
SMEN
28
20
12
4
-
-
-
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
-
AT32UC3L016/32/64
MDIS
25
17
9
1
-
-
-
STOP
MEN
24
16
8
0
-
-
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