AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 243
AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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13.7
32099F–11/2010
Module Configuration
The specific configuration for each SCIF instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks. Please refer to the Power Manager
chapter for details.
Table 13-7.
Table 13-8.
Table 13-9.
In AT32UC3L, there are six generic clocks. These are allocated to different functions as shown
in
Table 13-10. Generic Clock Allocation
Module Name
SCIF
Clock number
Table
STARTUP
GAIN[1:0]
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
13-10. Note that only GCLK4-0 are routed out.
MODULE Clock Name
Oscillator Startup Time
Oscillator
Number of System RC
oscillator clock cycle
0
64
128
2048
4096
8192
16384
Reserved
Oscillator is used with gain G0 (XIN from 0.45 MHz to 12.0 MHz)
Oscillator is used with gain G1 (XIN from 12.0 MHz to 16.0 MHz)
Oscillator is used with gain G2 (XIN equals 16.0 MHz. Used for e.g. increasing S/N
ratio, better drive strength for high ESR crystals)
Oscillator is used with gain G3 (XIN equals 16.0 MHz. Used for e.g. increasing S/N
ratio, better drive strength for high ESR crystals)
Clock Name
CLK_SCIF
Function
DFLLIF main reference and GCLK0 pin
(CLK_DFLLIF_REF)
DFLLIF dithering and ssg reference and GCLK1 pin
(CLK_DFLLIF_DITHER)
AST and GCLK2 pin
Gain Settings
Approximative Equivalent time
(RCSYS = 115 kHz)
0
560 us
1.1 ms
18 ms
36 ms
71 ms
142 ms
Reserved
Description
Clock for the SCIF bus interface
AT32UC3L016/32/64
243
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