AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 377

• Manufacturer Part Number: AT32UC3L064-AUT
• Description: MCU AVR32 64KB FLASH 48TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L064-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI/TWI/USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32099F–11/2010
In SPI Master Mode:
In SPI Slave Mode:
• the external clock CLK must not be selected (USCLKS … 0x3), and the bit CLKO must be set
• to obtain correct behavior of the receiver and the transmitter, the value programmed in CD of
• if the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must
• the external clock (CLK) selection is forced regardless of the value of the USCLKS field in the
• to obtain correct behavior of the receiver and the transmitter, the external clock (CLK)
to “1” in the Mode Register (MR), in order to generate correctly the serial clock on the CLK
pin.
must be superior or equal to 4.
be even to ensure a 50:50 mark/space ratio on the CLK pin, this value can be odd if the
internal clock is selected (CLK_USART).
Mode Register (MR). Likewise, the value written in BRGR has no effect, because the clock is
provided directly by the signal on the USART CLK pin.
frequency must be at least 4 times lower than the system clock.
AT32UC3L016/32/64
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