AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 531

• Manufacturer Part Number: AT32UC3L064-AUT
• Description: MCU AVR32 64KB FLASH 48TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L064-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI/TWI/USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23. Pulse Width Modulation Controller (PWMA)
23.1
23.2
32099F–11/2010
Features
Overview
Rev 1.0.1.0
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The Pulse Width Modulation Controller (PWMA) controls several pulse width modulation (PWM)
channels. The number of channels is specific to the device. Each channel controls one square
output PWM waveform. Characteristics of the output PWM waveforms such as period and duty
cycle are configured through the user interface. All user interface registers are mapped on the
peripheral bus.
The duty cycle value for each channel can be set independently, while the period is determined
by a common timebase counter (TC). The timebase for the counter is selected by using the allo-
cated asynchronous Generic Clock (GCLK). The user interface for the PWMA contains
handshake and synchronizing logic to ensure that no glitches occur on the output PWM wave-
forms while changing the duty cycle values.
PWMA duty cycle values can be changed using two approaches, either an interlinked single-
value mode or an interlinked multi-value mode. In the interlinked single-value mode, any set of
channels, up to 32 channels, can be updated simultaneously with the same value while the other
channels remain unchanged. In the interlinked multi-value mode, up to 4 selected channels can
be updated with 4 different values while the other channels remain unchanged.
Some pins can be driven in open drain mode, allowing the PWMA to generate a 5V waveform
using an external pullup resistor.
Left-aligned non-inverted 8-bit PWM
Common 8-bit timebase counter
Separate 8-bit duty cycle register per channel
Synchronized channel updates
Interlinked operation supported
Interrupt on PWM timebase overflow
Incoming peripheral events supported
One output peripheral event supported
Output PWM waveform for each channel
Open drain driving on selected pins for 5V PWM operation
– Asynchronous clock source supported
– Spread-spectrum counter to allow a constantly varying duty cycle
– No glitches when changing the duty cycles
– Multiple channels can be updated with the same duty cycle value at a time
– Up to four channels can be updated with different duty cycle values at a time
– Pre-defined channels support incoming (increase/decrease) peripheral events from the
– Increase event will increase the duty cycle by one
– Decrease event will decrease the duty cycle by one
– Connected to channel 0 and asserted when the common timebase counter is equal to the
Peripheral Event System
programmed duty cycle for channel 0
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