AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 289

• Manufacturer Part Number: AT32UC3L064-AUT
• Description: MCU AVR32 64KB FLASH 48TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L064-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI/TWI/USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 48TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16. External Interrupt Controller (EIC)
16.1
16.2
16.3
Figure 16-1. EIC Block Diagram
32099F–11/2010
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Block Diagram
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Rev: 3.0.1.0
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The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each
external interrupt has its own interrupt request and can be individually masked. Each external
interrupt can generate an interrupt on rising or falling edge, or high or low level. Every interrupt
input has a configurable filter to remove spikes from the interrupt source. Every interrupt pin can
also be configured to be asynchronous in order to wake up the part from sleep modes where the
CLK_SYNC clock has been disabled.
A Non-Maskable Interrupt (NMI) is also supported. This has the same properties as the other
external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any
other interrupt mode.
The EIC can wake up the part from sleep modes without triggering an interrupt. In this mode,
code execution starts from the instruction following the sleep instruction.
Dedicated interrupt request for each interrupt
Individually maskable interrupts
Interrupt on rising or falling edge
Interrupt on high or low level
Asynchronous interrupts for sleep modes without clock
Filtering of interrupt lines
Non-Maskable NMI interrupt
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