ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 277

MCU AVR 64K ISP FLASH 64-TQFP

ATMEGA64A-AU

Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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8160C–AVR–07/09
Table 25-7.
Bit Number
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
ATmega64A Boundary-scan Order (Continued)
Signal Name
RSTT
RSTHV
EXTCLKEN
OSCON
RCOSCEN
OSC32EN
EXTCLK (XTAL1)
OSCCK
RCCK
OSC32CK
TWIEN
PD0.Data
PD0.Control
PD0.Pullup_Enable
PD1.Data
PD1.Control
PD1.Pullup_Enable
PD2.Data
PD2.Control
PD2.Pullup_Enable
PD3.Data
PD3.Control
PD3.Pullup_Enable
PD4.Data
PD4.Control
PD4.Pullup_Enable
PD5.Data
PD5.Control
PD5.Pullup_Enable
PD6.Data
PD6.Control
PD6.Pullup_Enable
PD7.Data
PD7.Control
PD7.Pullup_Enable
PG0.Data
Module
Reset Logic
(Observe-only)
Enable Signals for Main Clock/Oscillators
Clock Input and Oscillators for the Main Clock
(Observe-only)
TWI
Port D
Port G
ATmega64A
277

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