ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 292

MCU AVR 64K ISP FLASH 64-TQFP

ATMEGA64A-AU

Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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26.8.13
8160C–AVR–07/09
ATmega64A Boot Loader Parameters
In
ming are given.
Table 26-6.
Note:
Table 26-7.
Note:
BOOTSZ1
Section
Read-While-Write (RWW)
No Read-While-Write (NRWW)
Table 26-6
Do_spm:
Wait_spm:
Wait_ee:
1
1
0
0
; check for previous SPM complete
lds
sbrc temp1, SPMEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in
cli
; check that no EEPROM write access is present
sbic EECR, EEWE
rjmp Wait_ee
; SPM timed sequence
sts
spm
; restore SREG (to enable interrupts if originally enabled)
out
ret
1. The different BOOTSZ Fuse configurations are shown in
1. For details about these two section, see
282
temp1, SPMCSR
temp2, SREG
SPMCSR, spmcrval
SREG, temp2
BOOTSZ0
through
Boot Size Configuration
Read-While-Write Limit
and
1
0
1
0
“RWW – Read-While-Write Section” on page 282
Table
Boot
Size
512
words
1024
words
2048
words
4096
words
26-8, the parameters used in the description of the Self-program-
Pages
16
32
()
4
8
(1)
Appli-
cation
Flash
Section
0x0000 -
0x7DFF
0x0000 -
0x7BFF
0x0000 -
0x77FF
0x0000 -
0x6FFF
“NRWW – No Read-While-Write Section” on page
Boot
Loader
Flash
Section
0x7E00 -
0x7FFF
0x7C00 -
0x7FFF
0x7800 -
0x7FFF
0x7000 -
0x7FFF
Pages
224
32
Figure 26-2
End
Applic-
ation
Section
0x7DFF
0x7BFF
0x77FF
0x6FFF
Address
0x0000 - 0x6FFF
0x7000 - 0x7FFF
ATmega64A
Boot Reset
Address
(Start Boot
Loader
Section)
0x7E00
0x7C00
0x7800
0x7000
292

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