ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 80

MCU AVR 64K ISP FLASH 64-TQFP

ATMEGA64A-AU

Manufacturer Part Number
ATMEGA64A-AU
Description
MCU AVR 64K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
53
Interface Type
SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
4
Processor Series
ATMEGA64x
Core
AVR8
Data Ram Size
4 KB
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Cpu Family
ATmega
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
For Use With
770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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13.3.4
8160C–AVR–07/09
Alternate Functions of Port D
Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0
Note:
The Port D pins with alternate functions are shown in
Table 13-12. Port D Pins Alternate Functions
Note:
The alternate pin configuration is as follows:
• T2 – Port D, Bit 7
T2, Timer/Counter2 Counter Source.
• T1 – Port D, Bit 6
T1, Timer/Counter1 Counter Source.
• XCK1 – Port D, Bit 5
XCK1, USART1 External Clock. The Data Direction Register (DDD5) controls whether the clock
is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1
operates in synchronous mode.
• ICP1 – Port D, Bit 4
ICP1 – Input Capture Pin1: The PD4 pin can act as an Input Capture pin for Timer/Counter1.
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Port Pin
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
1. XMM = 0 in ATmega103 compatibility mode.
1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode.
Alternate Function
T2 (Timer/Counter2 Clock Input)
T1 (Timer/Counter1 Clock Input)
XCK1
ICP1 (Timer/Counter1 Input Capture Pin)
INT3/TXD1
INT2/RXD1
INT1/SDA
INT0/SCL
PC3/A11
SRE • (XMM<5)
0
SRE • (XMM<5)
1
SRE • (XMM<5)
A11
0
0
(1)
(USART1 External Clock Input/Output)
(1)
(1)
(1)
(1)
(External Interrupt0 Input or TWI Serial CLock)
(External Interrupt1 Input or TWI Serial DAta)
(External Interrupt3 Input or UART1 Transmit Pin)
(External Interrupt2 Input or UART1 Receive Pin)
PC2/A10
SRE • (XMM<6)
0
SRE • (XMM<6)
1
SRE • (XMM<6)
A10
0
0
Table
PC1/A9
SRE • (XMM<7)
0
SRE • (XMM<7)
1
SRE • (XMM<7)
A9
0
0
13-12.
(1)
ATmega64A
PC0/A8
SRE • (XMM<7)
0
SRE • (XMM<7)
1
SRE • (XMM<7)
A8
0
0
80

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