ATMEGA64A-AU Atmel, ATMEGA64A-AU Datasheet - Page 340

• Manufacturer Part Number: ATMEGA64A-AU
• Description: MCU AVR 64K ISP FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 53
• Interface Type: SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• For Use With: 770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 28-15. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
8160C–AVR–07/09
0
10
12
14
15
16
Symbol
1/t
t
t
t
t
t
RLDV
RLRH
WHDX
DVWH
WLWH
CLCL
Parameter
Oscillator Frequency
Read Low to Data Valid
RD Pulse Width
Data Hold After WR High
Data Valid to WR High
WR Pulse Width
Figure 28-6. External Memory Timing (SRWn1 = 0, SRWn0 = 0
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0
A15:8
CPU
ALE
WR
RD
)
Prev. addr.
Prev. data
Min
735
485
750
735
4 MHz Oscillator
T1
1
Address
Address
4
2
Max
690
5
T2
6
3a
3b
XX
7
8
13
10
3.0t
2.0t
3.0t
Address
3.0t
T3
15
Min
CLCL
CLCL
CLCL
12
0.0
Data
Data
16
Variable Oscillator
CLCL
9
-15
-15
-15
11
ATmega64A
T4
3.0t
14
Max
CLCL
8
-60
MHz
Unit
ns
ns
ns
ns
ns
340