ATMEGA644V-10MU Atmel, ATMEGA644V-10MU Datasheet
ATMEGA644V-10MU
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ATMEGA644V-10MU Summary of contents
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... Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF • Speed Grades – ATmega644V MHz @ 1.8V - 5.5V MHz @ 2.7V - 5.5V – ATmega644 MHz @ 2.7V - 5.5V MHz @ 4.5V - 5.5V • Power Consumption at 1 MHz, 3V, 25⋅C – Active: 240 µA @ 1.8V, 1 MHz – ...
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Pin Configurations Figure 1-1. Note: ATmega644 2 Pinout ATmega644 (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/INT0) PD2 (PCINT27/INT1) PD3 (PCINT28/OC1B) ...
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Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2. Overview The ATmega644 ...
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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega644 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. The ATmega644 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits ...
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As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not ...
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AVCC AVCC is the supply voltage pin for Port F and the Analog-to-digital Converter. It should be exter- nally connected through a low-pass filter. CC 2.2.11 AREF This is the analog reference pin for the ...
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... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 2593N–AVR–07/10 ATmega644 7 ...
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About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in ...
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AVR CPU Core 5.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C ...
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The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 5-4 vard architecture and the fast-access Register ...
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RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep ...
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AVR Memories This section describes the different memories in the ATmega644. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega644 features an EEPROM Memory for data storage. All ...
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SRAM Data Memory Figure 6-2 on page 18 The ATmega644 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended ...
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Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 6-3. 6.3 EEPROM Data Memory The ATmega644 contains 2 Kbytes of data ...
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Preventing EEPROM Corruption During periods of low V too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. ...
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Register Description 6.5.1 EEARH and EEARL – The EEPROM Address Register Bit 0x22 (0x42) 0x21 (0x41) Read/Write Initial Value • Bits 15:12 – Res: Reserved Bits These bits are reserved bits in the ATmega644 and will always read as ...
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Table 6-1. EEPM1 • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The ...
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Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a ...
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Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value Note: ATmega644 MSB R/W R/W R SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 ...
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System Clock and Clock Options 7.1 Clock Systems and their Distribution Figure 7-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
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Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 7.1.4 Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous ...
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Table 7-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual ...
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Low Power Crystal Oscillator This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 out- put. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be ...
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Table 7-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 7.4 Full Swing Crystal Oscillator This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the ...
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Table 7-6. Oscillator Source / Power Conditions Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 7.5 Low Frequency Crystal Oscillator The device can utilize a 32.768 kHz watch ...
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Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See on page 319 with the CKDIV8 Fuse ...
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Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- quency is nominal at 3V and 25⋅C. This clock may be select as the system clock by ...
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External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 7-3. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 7-3. When this ...
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Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir- ...
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Register Description 7.12.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from ...
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This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. Note that any ...
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Power Management and Sleep Modes 8.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to ...
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Idle Mode When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Inter- face, Timer/Counters, Watchdog, and the interrupt ...
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Power-save Mode When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power- save mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 is enabled, it will keep running during sleep. ...
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Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis- abled before entering any sleep mode. When the ADC is turned off and on again, the ...
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DIDR0). Refer to Input Disable Register 0” on page 252 8.10.7 On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode, the main clock source is enabled, and hence, always ...
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PRR – Power Reduction Register Bit (0x64) Read/Write Initial Value • Bit 7 - PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up ...
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System Control and Reset 9.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 9-1. BODLEVEL [2..0] 9.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to trigger the ...
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Figure 9-3. TIME-OUT INTERNAL 9.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is not running. Shorter pulses are ...
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Figure 9-5. 9.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t ”Watchdog Timer” ...
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Watchdog Timer ATmega644 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16 ...
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In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four ...
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Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this ...
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Register Description 9.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x34 (0x54) Read/Write Initial Value • Bit 4 – JTRF: JTAG Reset Flag This bit is ...
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If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes ...
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Table 9-2. WDP3 ATmega644 54 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 512K (524288) cycles 1024K (1048576) cycles ...
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Interrupts This section describes the specifics of the interrupt handling as performed in ATmega644. For a general explanation of the AVR interrupt handling, refer to page 14. 10.1 Interrupt Vectors in ATmega644 Table 10-1. Vector No ...
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Notes: Table 10-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8 Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are ...
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When the BOOTRST Fuse is programmed, the Boot section size set to 8 Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup ...
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IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written ...
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External Interrupts The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as outputs. This feature provides ...
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Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled. Table 11-1. ISCn1 Note: Table 11-2. Symbol t INT 11.1.2 EIMSK – External Interrupt Mask ...
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PCICR – Pin Change Interrupt Control Register Bit (0x68) Read/Write Initial Value • Bit 3 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set ...
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Bit 1 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), ...
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PCMSK0 – Pin Change Mask Register 0 Bit (0x6B) Read/Write Initial Value • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7..0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 ...
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I/O-Ports 12.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 12.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 12-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...
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Assembly Code Example C Code Example unsigned char i; Note: 12.2.5 Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, ...
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Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...
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Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified alternate functions. The overriding signals may not be present in all port pins, ...
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Table 12-2 ure 12-5 in the modules having the alternate function. Table 12-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the ...
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Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 12-3. Port Pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 • ADC7:0/PCINT7:0 ...
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Table 12-4 shown in Table 12-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 12-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega644 74 and Table 12-5 relates the alternate ...
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Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 12-6. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • SCK/PCINT15 – Port B, ...
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MOSI/PCINT13 – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When ...
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T0/XCK0/PCINT8, Bit 0 T0, Timer/Counter0 counter source. XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the USART0 operates ...
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Alternate Functions of Port C The Port C alternate function is as follows: Table 12-9. Port Pin PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 • TOSC2/PCINT23 – Port C, Bit 7 TOSC2, Timer Oscillator pin 2. The PC7 ...
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TMS/PCINT19 – Port C, Bit 3 TMS, JTAG Test Mode Select. PCINT19, Pin Change Interrupt source 19: The PC3 pin can serve as an external interrupt source. • TCK/PCINT18 – Port C, Bit 2 TCK, JTAG Test Clock. PCINT18, ...
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Table 12-11. Overriding Signals for Alternate Functions in PC3:PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 12.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 12-12. Port ...
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OC2A/PCINT31 – Port D, Bit 7 OC2A, Output Compare Match A output: The PD7 pin can serve as an external output for the Timer/Counter2 Output Compare A. The pin has to be configured as an output (DDD7 set (one)) ...
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INT0/PCINT26 – Port D, Bit 2 INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the MCU. PCINT26, Pin Change Interrupt Source 26: The PD2 pin can serve as an external interrupt ...
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Table 12-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: 2593N–AVR–07/10 PD3/INT1/ PD2/INT0/ PCINT27 PCINT26 0 0 PORTD2 • PUD 0 RXEN1 ...
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Register Description 12.3.5 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn ...
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PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 12.3.13 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 12.3.14 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial ...
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Timer/Counter0 with PWM 13.1 Feature • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period ...
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The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR0A and ...
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Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source ...
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Figure 13-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...
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Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...
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Figure 13-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com- pare Matches between OCR0x and TCNT0. Figure 13-6. Fast PWM ...
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OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 13.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = ...
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OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See visible on the port pin if the data direction for the port pin is ...
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Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 13-10 mode and PWM mode, where OCR0A is TOP. Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk I/O TCNTn ...
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Register Description 13.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...
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Table 13-4 rect PWM mode. Table 13-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits ...
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Note: Table 13-4 rect PWM mode. Table 13-7. COM0A1 Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega644 and will always read as zero. • Bits 1:0 – WGM01:0: ...
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TCCR0B – Timer/Counter Control Register B Bit 0x25 (0x45) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility ...
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Table 13-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control ...
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Bits 7:3 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the ...
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The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 2593N–AVR–07/10 ATmega644 Table 99. 13-8, ”Waveform 103 ...
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Timer/Counter1 with PWM 14.1 Features • True 16-bit Design (that is, allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear ...
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Figure 14-1. 16-bit Timer/Counter Block Diagram Note: 14.2.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...
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See Section “14.7” on page Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture ...
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Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNTn value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...
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The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: ; Save global interrupt ...
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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example void ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 14-2 Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...
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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 14.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
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TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written ...
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I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 14.7 Output Compare Units The 16-bit comparator continuously compares ...
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PWM pulses, thereby making the out- put glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer ...
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Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1 tells the Waveform Generator that no action on the OCnx Register ...
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The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 14-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can ...
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PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), ...
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ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will ...
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However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or defined by ...
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OCRnx Registers are written. As the third period shown in TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update ...
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OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...
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Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively ...
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Figure 14-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f (clk TCNTn OCRnx OCFnx Figure 14-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced ...
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Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 14.11 Register Description 14.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 ...
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Table 14-3 PWM mode. Table 14-3. COMnA1/COMnB1 Note: Table 14-4 correct or the phase and frequency correct, PWM mode. Table 14-4. COMnA1/COMnB1 Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB ...
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Table 14-5. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...
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When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...
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A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 14.11.4 TCNT1H and TCNT1L –Timer/Counter1 Bit ...
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ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator ...
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TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega644, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, ...
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Timer/Counter2 with PWM and Asynchronous Operation 15.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and ...
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Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer ...
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Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Figure 15-3. Output Compare Unit, Block Diagram The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...
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The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com- pare (FOC2x) strobe bit in ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1 tells the Waveform Generator that no action on the OC2x Register ...
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Figure 15-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in shown as ...
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OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 15.7.4 Phase Correct PWM Mode ...
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COM2x1:0 to three. TOP is defined as 0xFF when WGM2 and OCR2A when MGM2 (See value will only be visible on the port pin if the data direction for ...
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Figure 15-9 Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 15-10 Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 15-11 ATmega644 142 shows the ...
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Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- (clk TCNTn (CTC) OCRnx OCFnx 15.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous ...
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TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is ...
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Timer/Counter Prescaler Figure 15-12. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, ...
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Register Description 15.11.1 TCCR2A – Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the ...
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Table 15-4 rect PWM mode. Table 15-4. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits ...
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Note: Table 15-7 rect PWM mode. Table 15-7. COM2B1 Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega644 and will always read as zero. • Bits 1:0 – WGM21:0: ...
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TCCR2B – Timer/Counter Control Register B– Bit (0xB1) Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with ...
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Table 15-9. CS22 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control ...
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Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf- fer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) ...
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TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit (0x70) Read/Write Initial Value • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is ...
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Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 15.11.9 GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value ...
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SPI – Serial Peripheral Interface 16.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
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The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 16-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...
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Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 2593N–AVR–07/10 (1) ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set clock ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi out ; Enable SPI ldi out ret SPI_SlaveReceive: ...
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SS Pin Functionality 16.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Table 16-2. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 16-3. SPI Transfer Format with CPHA = 0 Figure 16-4. SPI Transfer Format with CPHA = 1 ATmega644 160 CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) ...
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Register Description 16.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...
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Bits 1:0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK ...
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SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. ...
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USART 17.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...
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Figure 17-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...
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UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous ...
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Table 17-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode BAUD f OSC UBRRn Some examples of UBRRn values for some system clock frequencies are found in page 187. 17.3.2 ...
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External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter ...
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Figure 17-4 optional. Figure 17-4. Frame Formats St ( IDLE must be The frame format used by the USART ...
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USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. ...
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Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by ...
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Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following ...
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When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by ...
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UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp ...
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Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive ...
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Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...
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The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read ...
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Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no communication activity). Figure 17-5. Start Bit Sampling Sample (U2X = 0) ...
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Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 ...
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Table 17-2. # (Data+Parity Bit) Table 17-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...
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When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to ...
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Register Description 17.10.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...
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UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received, that is, ...
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Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, ...
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Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...
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Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and ...
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Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the UBRR settings in UBRR values which yield an actual baud rate differing ...
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Table 17-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
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Table 17-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
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Table 17-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
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USART in SPI Mode 18.1 Features • Full Duplex, Three-wire Synchronous Data Transfer • Master Operation • Supports all four SPI Modes of Operation (Mode and 3) • LSB First or MSB First Data Transfer (Configurable ...
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Table 18-1. Operating Mode Synchronous Master mode Note: BAUD f OSC UBRRn 18.4 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn ...
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Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: • 8-bit data with MSB first • 8-bit data with LSB ...
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Assembly Code Example USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn) out UCSRnC,r18 ...
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The data written to UDRn is moved from the transmit buf- fer to the shift register when the shift register is ready to send a new frame. Note: The following code examples show a simple ...
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Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) ...
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UCSRnB – USART MSPIM Control and Status Register n B Bit Read/Write Initial Value • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt ...
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Bit 7:6 - UMSELn1:0: USART Mode Select These bits select the mode of operation of the USART as shown in USART Control and Status Register n C” on page 184 operation. The MSPIM is enabled when both UMSELn bits ...
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AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: • Master mode timing diagram. • The UCPOLn bit functionality is identical to the SPI CPOL bit. • The UCPHAn ...
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Serial Interface 19.1 Features • Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows up ...