ATMEGA644V-10MU Atmel, ATMEGA644V-10MU Datasheet - Page 77

• Manufacturer Part Number: ATMEGA644V-10MU
• Description: IC AVR MCU FLASH 64K 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Package: 44QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: JTAG/SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2593N–AVR–07/10
• T0/XCK0/PCINT8, Bit 0
T0, Timer/Counter0 counter source.
XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock
is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the
USART0 operates in Synchronous mode.
PCINT8, Pin Change Interrupt source 8: The PB0 pin can serve as an external interrupt source.
Table 12-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. .
Table 12-7.
Table 12-8.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 12-5 on page
PB7/SCK/
PCINT15
SPE • MSTR
PORTB7 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
PCINT15 • PCIE1
1
SCK INPUT
PCINT17 INPUT
–
PB3/AIN1/OC0B/
PCINT11
0
0
0
0
OC0B ENABLE
OC0B
PCINT11 • PCIE1
1
PCINT11 INPUT
–
and
Overriding Signals for Alternate Functions in PB7:PB4
Overriding Signals for Alternate Functions in PB3:PB0
Table 12-8
relate the alternate functions of Port B to the overriding signals
71. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB6/MISO/
PCINT14
SPE • MSTR
PORTB14 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE
OUTPUT
PCINT14 • PCIE1
1
SPI MSTR INPUT
PCINT14 INPUT
–
PB2/AIN0/INT2/
PCINT10
0
0
0
0
0
0
INT2 ENABLE
PCINT10 • PCIE1
1
INT2 INPUT
PCINT10 INPUT
–
PB5/MOSI/
PCINT13
SPE • MSTR
PORTB13 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR OUTPUT
PCINT13 • PCIE1
1
SPI SLAVE INPUT
PCINT13 INPUT
–
PB1/T1/CLKO/PCIN
T9
0
0
0
0
0
0
PCINT9 • PCIE1
1
T1 INPUT
PCINT9 INPUT
–
ATmega644
PB4/SS/OC0B/
PCINT12
SPE • MSTR
PORTB12 • PUD
SPE • MSTR
0
OC0A ENABLE
OC0A
PCINT4 • PCIE1
1
SPI SS
PCINT12 INPUT
–
PB0/T0/XCK/
PCINT8
0
0
0
0
0
0
PCINT8 • PCIE1
1
T0 INPUT
PCINT8 INPUT
–
77