ATMEGA644V-10MU Atmel, ATMEGA644V-10MU Datasheet - Page 280

• Manufacturer Part Number: ATMEGA644V-10MU
• Description: IC AVR MCU FLASH 64K 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Package: 44QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: JTAG/SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.8.14
In
Table 24-7.
The different BOOTSZ Fuse configurations are shown in
Table 24-8.
Note:
280
BOOTSZ1
Section
Read-While-Write section (RWW)
No Read-While-Write section (NRWW)
Table 24-7
1
1
0
0
1. For details about these two section, see
ATmega644
ATmega644 Boot Loader Parameters
Write Section” on page
BOOTSZ0
through
Boot Size Configuration
Read-While-Write Limit
1
0
1
0
Table
1024 words
2048 words
4096 words
Boot Size
Note:
512 words
24-9, the parameters used in the description of the Self-Programming are given.
Do_spm:
Wait_spm:
Wait_ee:
ret
; re-enable the RWW section
ldi
call Do_spm
rjmp Return
; check for previous SPM complete
in
sbrc temp1, SPMEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in
cli
; check that no EEPROM write access is present
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out
spm
; restore SREG (to enable interrupts if originally enabled)
out
ret
270.
1. For details about these two section, see
270
(1)
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
temp1, SPMCSR
temp2, SREG
SPMCSR, spmcrval
SREG, temp2
Pages
and
16
32
4
8
”RWW – Read-While-Write Section” on page
”NRWW – No Read-While-Write Section” on page 270
Application
Flash Section
0x0000 - 0x7DFF
0x0000 - 0x7BFF
0x0000 - 0x77FF
0x0000 - 0x6FFF
Pages
224
32
Figure
24-2.
Boot Loader
Flash Section
0x7E00 - 0x7FFF
0x7C00 - 0x7FFF
0x7800 - 0x7FFF
0x7000 - 0x7FFF
Address
0x0000 - 0x6FFF
0xF000 - 0x7FFF
”NRWW – No Read-While-Write Section” on page
270.
End Application
Section
0x7DFF
0x7BFF
0x77FF
0x6FFF
and
”RWW – Read-While-
Boot Reset
Address
(Start Boot
Loader
Section)
0x7E00
0x7C00
0x7800
0x7000
2593N–AVR–07/10