ATMEGA644V-10MU Atmel, ATMEGA644V-10MU Datasheet - Page 131

• Manufacturer Part Number: ATMEGA644V-10MU
• Description: IC AVR MCU FLASH 64K 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Package: 44QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: JTAG/SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.11.9
2593N–AVR–07/10
TIFR1 – Timer/Counter1 Interrupt Flag Register
• Bit 7:6 – Res: Reserved Bits
These bits are unused bits in the ATmega644, and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the coun-
ter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4:3 – Res: Reserved Bits
These bits are unused bits in the ATmega644, and will always read as zero.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOV1 Flag is set when the timer overflows. Refer to
Flag behavior when using another WGMn3:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
Bit
0x16 (0x36)
Read/Write
Initial Value
R
7
–
0
R
6
–
0
ICF1
R/W
5
0
R
4
–
0
R
3
–
0
Table 14-5 on page 127
OCF1B
R/W
2
0
OCF1A
R/W
1
0
ATmega644
TOV1
R/W
0
0
for the TOV1
TIFR1
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