MC9S12XEG128MAA Freescale Semiconductor, MC9S12XEG128MAA Datasheet - Page 258
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MC9S12XEG128MAA
Manufacturer Part Number
MC9S12XEG128MAA
Description
MCU 16BIT 128K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEG128MAA
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 12x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-QFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
59
Number Of Timers
25
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
No. Of I/o's
59
Eeprom Memory Size
2KB
Ram Memory Size
12KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
QFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 5 External Bus Interface (S12XEBIV4)
Read data are not captured in emulation expanded mode until the specified setup time before the falling
edge of ECLK.
In emulation expanded mode, accesses to the internal flash or the emulation memory (determined by
EROMON and ROMON bits; see S12X_MMC section for details) always take 1 cycle and stretching is
not supported. In case the internal flash is taken out of the map in user applications, accesses are stretched
as programmed and controlled by external wait.
5.4.5
The S12X_EBI supports byte and word accesses at any valid external address. The big endian system of
the MCU is extended to the external bus; however, word accesses are restricted to even aligned addresses.
The only exception is the visibility of misaligned word accesses to addresses in the internal RAM as this
module exclusively supports these kind of accesses in a single cycle.
With the above restriction, a fixed relationship is implied between the address parity and the dedicated bus
halves where the data are accessed: DATA[15:8] is related to even addresses and DATA[7:0] is related to
odd addresses.
In expanded modes the data access type is externally determined by a set of control signals, i.e., data select
and data direction signals, as described below. The data select signals are not available if using the external
bus interface with an 8-bit data bus.
5.4.5.1
In normal expanded mode, the external signals RE, WE, UDS, LDS indicate the access type (read/write),
data size and alignment of an external bus access
5.4.5.2
In emulation modes and special test mode, the external signals LSTRB, RW, and ADDR0 indicate the
access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the
258
Word write of data on DATA[15:0] at an even and even+1 address
Byte write of data on DATA[7:0] at an odd address
Byte write of data on DATA[15:8] at an even address
Word read of data on DATA[15:0] at an even and even+1 address
Byte read of data on DATA[7:0] at an odd address
Byte read of data on DATA[15:8] at an even address
Indicates No Access
Unimplemented
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Data Select and Data Direction Signals
Normal Expanded Mode
Emulation Modes and Special Test Mode
Access
Table 5-19. Access in Normal Expanded Mode
MC9S12XE-Family Reference Manual , Rev. 1.23
(Table
5-19).
RE WE UDS LDS
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
1
0
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
Out data(even) Out data(odd)
Out data(even)
I/O data(addr) I/O data(addr)
In
In
In
In
In
In
In
DATA[15:8]
data(even)
data(even)
Freescale Semiconductor
x
x
x
x
x
Out data(odd)
In
In
In
In
In
In
In
DATA[7:0]
data(odd)
data(odd)
x
x
x
x
x
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