MC9S12XEG128MAA Freescale Semiconductor, MC9S12XEG128MAA Datasheet - Page 746
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MC9S12XEG128MAA
Manufacturer Part Number
MC9S12XEG128MAA
Description
MCU 16BIT 128K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEG128MAA
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 12x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-QFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
59
Number Of Timers
25
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
No. Of I/o's
59
Eeprom Memory Size
2KB
Ram Memory Size
12KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
QFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 20 Serial Communication Interface (S12SCIV5)
The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the
buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by
writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting
out the first byte.
To initiate an SCI transmission:
Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic
1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from
the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit
position.
Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data
character is the parity bit.
The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI
data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data
register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI
control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request.
746
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
1. Configure the SCI:
2. Transmit Procedure for each byte:
3. Repeat step 2 for each subsequent transmission.
a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud
b) Write to SCICR1 to configure word length, parity, and other configuration bits
c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2
a) Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind
b) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is
rate generator. Remember that the baud rate generator is disabled when the baud rate is zero.
Writing to the SCIBDH has no effect without also writing to SCIBDL.
(LOOPS,RSRC,M,WAKE,ILT,PE,PT).
register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now
be shifted out of the transmitter shift register.
that the TDRE bit resets to one.
written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not
result until the TDRE flag has been cleared.
The TDRE flag is set when the shift register is loaded with the next data to
be transmitted from SCIDRH/L, which happens, generally speaking, a little
over half-way through the stop bit of the previous frame. Specifically, this
transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the
previous frame.
MC9S12XE-Family Reference Manual , Rev. 1.23
NOTE
Freescale Semiconductor
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