MC9S12XEG128MAA Freescale Semiconductor, MC9S12XEG128MAA Datasheet - Page 334
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MC9S12XEG128MAA
Manufacturer Part Number
MC9S12XEG128MAA
Description
MCU 16BIT 128K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEG128MAA
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 12x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-QFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
59
Number Of Timers
25
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
No. Of I/o's
59
Eeprom Memory Size
2KB
Ram Memory Size
12KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
QFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 8 S12X Debug (S12XDBGV3) Module
this triggers the state sequencer into the Final State, if configured for end alignment, setting the TRIG bit
disarms the module, ending the session. If breakpoints are enabled, a forced breakpoint request is issued
immediately (end alignment) or when tracing has completed (begin or mid alignment).
8.4.3.6
In case of simultaneous triggers, the priority is resolved according to
is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger
of a higher priority. The trigger priorities described in
matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that
a match leading to final state has priority over all other matches in each state sequencer state. When
configured for range modes a simultaneous match of comparators A and C generates an active match0
whilst match2 is suppressed.
If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm
from an internal trigger event, then the ARM bit is cleared due to the hardware disarm.
8.4.4
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register,
334
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Highest
Priority
Lowest
State Sequence Control
Trigger Priorities
(Disarmed)
Match0 (force or tag hit)
Match1 (force or tag hit)
Match2 (force or tag hit)
Match3 (force or tag hit)
State 0
ARM = 0
External TAGHI/TAGLO
XGATE BKP
Source
ARM = 0
TRIG
Session Complete
MC9S12XE-Family Reference Manual , Rev. 1.23
(Disarm)
ARM = 1
ARM = 0
Figure 8-22. State Sequencer Diagram
Table 8-42. Trigger Priorities
Trigger immediately to final state (begin or mid aligned tracing enabled)
Immediate forced breakpoint......(Tracing terminated immediately).
Trigger immediately to state 0 (end aligned or no tracing enabled)
Final State
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Table 8-42
State1
dictate that in the case of simultaneous
Table
Enter State0
State3
Action
8-42. The lower priority trigger
State2
Freescale Semiconductor
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