MC9S12XEG128MAA Freescale Semiconductor, MC9S12XEG128MAA Datasheet - Page 635

• Manufacturer Part Number: MC9S12XEG128MAA
• Description: MCU 16BIT 128K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEG128MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 25
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• No. Of I/o's: 59
• Eeprom Memory Size: 2KB
• Ram Memory Size: 12KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: QFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read:
Write:
Reset: Undefined because of RAM-based implementation
16.3.3.1
The identifier registers for an extended format identifier consist of a total of 32 bits: ID[28:0], SRR, IDE,
and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0],
RTR, and IDE.
Freescale Semiconductor
Register
Register
0x00X0
0x00X1
0x00X2
0x00X3
•
•
•
•
Name
Name
IDR0
IDR1
IDR2
IDR3
For transmit buffers, anytime when TXEx flag is set (see
Flag Register
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
For receive buffers, only when RXF flag is set (see
Register
For transmit buffers, anytime when TXEx flag is set (see
Flag Register
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
Unimplemented for receive buffers.
Figure 16-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued)
Identifier Registers (IDR0–IDR3)
Figure 16-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
W
W
W
W
R
R
R
R
(CANRFLG)”).
Bit 7
Bit 7
ID10
ID2
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
= Unused, always read ‘x’
= Unused, always read ‘x’
MC9S12XE-Family Reference Manual Rev. 1.23
ID9
ID1
6
6
ID8
ID0
5
5
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
RTR
ID7
4
4
Section 16.3.2.5, “MSCAN Receiver Flag
IDE (=0)
Section 16.3.2.7, “MSCAN Transmitter
Section 16.3.2.7, “MSCAN Transmitter
ID6
3
3
(CANTBSEL)”).
(CANTBSEL)”).
ID5
2
2
ID4
1
1
Bit 0
Bit0
ID3
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