MC9S12XEG128MAA Freescale Semiconductor, MC9S12XEG128MAA Datasheet - Page 852
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MC9S12XEG128MAA
Manufacturer Part Number
MC9S12XEG128MAA
Description
MCU 16BIT 128K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XEP768CAL.pdf
(1328 pages)
Specifications of MC9S12XEG128MAA
Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 12x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-QFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
59
Number Of Timers
25
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 12-bit
No. Of I/o's
59
Eeprom Memory Size
2KB
Ram Memory Size
12KB
Cpu Speed
50MHz
No. Of Timers
3
No. Of Pwm Channels
8
Digital Ic Case Style
QFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)
24.3.2.8
The FERSTAT register reflects the error status of internal Flash operations.
All flags in the FERSTAT register are readable and only writable to clear the flag.
852
MGSTAT[1:0]
MGBUSY
ACCERR
Offset Module Base + 0x0007
Reset
FPVIOL
RSVD
Field
CCIF
1–0
7
5
4
3
2
W
R
ERSERIF
Flash Error Status Register (FERSTAT)
7
0
Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see
command or when errors are encountered while initializing the EEE buffer ram during the reset sequence.
While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by
writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash memory during a command write sequence. The FPVIOL bit is cleared
by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL is set, it is not
possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0) or is handling internal EEE operations
Reserved Bit — This bit is reserved and always reads 0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
is detected during execution of a Flash command or during the Flash reset sequence. See
“Flash Command
= Unimplemented or Reserved
PGMERIF
0
6
Figure 24-12. Flash Error Status Register (FERSTAT)
Description,” and
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 24-17. FSTAT Field Descriptions
0
0
5
Section 24.6,
EPVIOLIF
0
4
Description
“Initialization” for details.
ERSVIF1
.
0
3
Section
ERSVIF0
0
2
24.4.1.2) or issuing an illegal Flash
Freescale Semiconductor
DFDIF
0
1
Section 24.4.2,
SFDIF
0
0
.
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