UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 155

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UPD70F3735GC-GAD-AX

Manufacturer Part Number
UPD70F3735GC-GAD-AX
Description
MCU 32BIT V850ES/JX3-L 80-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3735GC-GAD-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
66
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3735GC-GAD-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JF3-L
5.4
5.4.1
5.4.2
can be set to 8 bits and 16 bits only.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Bus Cycle Type
Instruction fetch (normal access)
Instruction fetch (branch)
Operand data access
The following table shows the number of basic clocks required for accessing each resource.
Note Increases by 1 if a conflict with a data access occurs.
Remark
Each external memory area selected by memory block n can be set by using the BSC register. However, the bus size
The external memory area of the V850ES/JF3-L is selected by memory blocks 0 to 3.
(1) Bus size configuration register (BSC)
Bus Access
The BSC register can be read or written in 16-bit units.
Reset sets this register to 5555H.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not access
Number of clocks for access
Bus size setting function
Caution Be sure to set bits 14, 12, 10, and 8 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to “0”.
Unit: Clocks/access
an external memory area until the initial settings of the BSC register are complete.
After reset:
BSC
Area (Bus Width)
BSn0
15
5555H
0
0
0
1
7
Memory block 3
8 bits
16 bits
BS30
14
1
6
R/W
Data bus width of
Internal ROM (32 Bits)
Address:
13
0
0
5
1
2
3
Memory block 2
memory block n
BS20
FFFFF066H
12
1
4
11
0
0
3
Internal RAM (32 Bits)
space (n = 0 to 3)
Memory block 1
CHAPTER 5 BUS CONTROL FUNCTION
BS10
10
1
2
1
2
Note
Note
1
0
0
9
1
Memory block 0
External Memory (16 Bits)
BS00
1
8
0
3 + n
3 + n
3 + n
Page 139 of 816

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