UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 463

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
15.6.5 UART transmission
writing transmit data to the UAnTX register. The start bit, parity bit, and stop bit are automatically added.
enabled at the transmit destination.
operation.
the UAnTX register to the UARTAn transmit shift register, and thereafter the contents of the UARTAn transmit shift register
are output to the TXDAn pin.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1.
Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by
Since the CTS (transmit enable signal) input pin is not provided in UARTAn, use a port to check that reception is
The data in the UAnTX register is transferred to the UARTAn transmit shift register upon the start of the transmit
A transmission enable interrupt request signal (INTUAnT) is generated upon completion of transmission of the data of
Write of the next transmit data to the UAnTX register is enabled after the INTUAnT signal is generated.
Remark
TXDAn
INTUAnT
LSB first
Start
bit
D0
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Figure 15-8. UART Transmission
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit
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