UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 772

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
Main Clock Oscillator Characteristics
(T
Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/JF3-L so that
Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Ceramic
resonator/
Crystal
resonator
Resonator
A
= −40 to +85°C, V
2. Time required from start of oscillation until the resonator stabilizes.
3. The oscillation stabilization time differs depending on the set value of the option byte. For details, see
4. The oscillation stabilization time after reset release is restricted in accordance with the set value of the option
5. Time required to set up the regulator and flash memory. Secure the setup time using the OSTS register.
6. The value varies depending on the setting of the OSTS register.
7. Time required to set up the regulator, flash memory, and PLL. Secure the setup time using the OSTS register.
2. When the main clock is stopped and the device is operating on the subclock, wait until the
the internal operation conditions do not exceed the ratings shown in AC Characteristics and DC
Characteristics.
CHAPTER 27 OPTION BYTE.
byte. For details, see CHAPTER 27 OPTION BYTE.
above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as V
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
oscillation stabilization time has been secured by the program before switching back to the main
clock.
Circuit Example
X1
DD
= EV
X2
DD
= AV
REF0
Oscillation frequency
(f
Oscillation
stabilization
time
X
)
Note 1
Note 2
= AV
Parameter
REF1
, V
SS
= EV
Clock through
mode
V
V
released
After STOP
mode is
released
After IDLE2
mode is
released
DD
DD
SS
= 2.7 to 3.6 V in PLL mode
= 2.2 to 3.6 V after reset is
= AV
SS
CHAPTER 30 ELECTRICAL SPECIFICATIONS
Conditions
= 0 V)
V
V
V
in clock through
mode
V
in PLL mode
V
in clock through
mode
V
in PLL mode
DD
DD
DD
DD
DD
DD
= 2.7 to 3.6 V
= 2.2 to 3.6 V
= 2.7 to 3.6 V
= 2.2 to 3.6 V
= 2.7 to 3.6 V
= 2.2 to 3.6 V
350
800
Note 3 Note 4
MIN.
1
1
2.5
2.5
2.5
Note 5
Note 7
Note 5
Note 7
Note 6
Note 6
Note 6
Note 6
TYP.
SS
MAX.
.
10
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5
5
MHz
MHz
MHz
Unit
ms
ms
μ
μ
s
s
s