UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 72

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
3.4.8
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
(1) Registers to be set first
Be sure to set the following registers first when using the V850ES/JF3-L.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM)
• Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related
registers after setting the above registers.
(a) System wait control register (VSWC)
(b) On-chip debug mode register (OCDM)
(c) Watchdog timer mode register 2 (WDTM2)
Cautions
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.
Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The V850ES/JF3-
L requires wait cycles according to the operating frequency. Set the following value to the VSWC register in
accordance with the frequency used.
The VSWC register can be read or written in 8-bit units (address: FFFFF06EH, default value: 77H).
For details, see CHAPTER 29 ON-CHIP DEBUG FUNCTION.
The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.
Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register to
activate this operation.
For details, see CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2.
32 kHz ≤ f
16.6 MHz ≤ f
Operating Frequency (f
CLK
CLK
< 16.6 MHz
≤ 20 MHz
CLK
)
Set Value of VSWC
00H
01H
Number of Waits
0 (no waits)
CHAPTER 3 CPU FUNCTION
1
Page 56 of 816