UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 166

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
5.5.4
wait insertion is set for each memory block area (memory blocks 0 to 3).
address hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address
If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock. If an
(1) Address wait control register (AWC)
The AWC register can be read or written in 16-bit units.
Reset sets this register to FFFFH.
Cautions 1. Address setup wait and address hold wait cycles are not inserted when the internal ROM area,
Programmable address wait function
Caution Be sure to set bits 15 to 8 to “1”.
2. Write to the AWC register after reset, and then do not change the set values. Also, do not
After reset:
AWC
internal RAM area, and on-chip peripheral I/O areas are accessed.
access an external memory area until the initial settings of the AWC register are complete.
AHW3
AHWn
ASWn
Memory block 3
15
FFFFH
1
0
1
0
1
7
Not inserted
Inserted
Not inserted
Inserted
ASW3
14
1
6
R/W
Specifies insertion of address setup wait (n = 0 to 3)
Specifies insertion of address hold wait (n = 0 to 3)
AHW2
Memory block 2
13
Address:
1
5
ASW2
FFFFF488H
12
1
4
AHW1
Memory block 1
11
1
3
CHAPTER 5 BUS CONTROL FUNCTION
ASW1
10
1
2
AHW0
Memory block 0
1
9
1
ASW0
1
8
0
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