UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 34

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
2.2
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
P05/DRST
P10/ANO0
P53/DDO
AD0 to AD15
A16, A17
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDAK
HLDRQ
Other port pins
The operation states of pins in the various modes are described below.
Notes 1. Duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit)
Remark
Pin Name
Pin States
2. Operates while an alternate function is operating.
3. The state of the pins in the idle state inserted after the T3 state is shown.
4. Pulled down during external reset. During internal reset by the watchdog timer, clock monitor, etc., the state
5. DDO output is specified in the on-chip debug mode.
6. The bus control pins function alternately as port pins, so they are initialized to the input mode (port mode).
7. Operates even in the HALT mode, during DMA operation.
when the power is turned on.
of this pin differs according to the OCDM.OCDM0 bit setting.
Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L:
H:
−:
When Power
Pulled down
Undefined
Low-level output
High-level output
Input without sampling (not acknowledged)
Is Turned
Hi-Z
On
Hi-Z
Note 1
Note 6
Pulled down
(Except When
During Reset
Table 2-2. Pin Operation States in Various Modes
Turned On)
Power Is
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note 5
Note 6
Note 4
HALT Mode
Undefined
Operating
Operating
H
Held
Held
Held
Held
Note 7
−
Note 7
Note 7
Note 2
IDLE1, IDLE2,
Sub-IDLE
Mode
Held
Held
Held
Held
Hi-Z
H
−
L
−
Note 2
Mode
STOP
Held
Held
Held
Hi-Z
Hi-Z
H
CHAPTER 2 PIN FUNCTIONS
−
L
−
Note 2
Operating
State
Held
Held
Held
Held
Held
Idle
H
−
−
Note 3
Operating
Operating
Bus Hold
Page 18 of 816
Held
Held
Held
Held
Hi-Z
Hi-Z
−
L