UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 611

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
(3) DMA transfer count registers 0 to 3 (DBC0 to DBC3)
Cautions 1. Set the DBCn register at the following timing when DMA transfer is disabled (DCHCn.Enn
The DBC0 to DBC3 registers are 16-bit registers that set the transfer count for DMA channel n (n = 0 to 3). These
registers hold the remaining transfer count during DMA transfer.
These registers are decremented by 1 per one transfer regardless of the transfer data unit (8/16 bits), and the
transfer is terminated if a borrow occurs.
These registers can be read or written in 16-bit units.
2. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before
(n = 0 to 3)
DBCn
bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
starting DMA transfer. If these registers are not set, the operation when DMA transfer is
started is not guaranteed.
After reset:
DMA transfer
BC15
15
BC15 to
FFFFH
The number of transfer data set first is held when DMA transfer is complete.
0000H
0001H
Undefined
BC0
:
BC14
14
BC13
13
Transfer count 1 or remaining transfer count
Transfer count 2 or remaining transfer count
Transfer count 65,536 (2
Transfer count setting or remaining transfer count during DMA transfer
BC12
12
R/W
BC11
11
BC10
Address:
10
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
BC9
9
DBC0 FFFFF0C0H, DBC1 FFFFF0C2H,
16
DBC2 FFFFF0C4H, DBC3 FFFFF0C6H
BC8
) or remaining transfer count
8
BC7
7
:
BC6
6
BC5
5
BC4
4
BC3
3
BC2
2
BC1
1
BC0
0
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