UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 238

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
<1> Count operation start flow
(1) Operation flow in one-shot pulse output mode
Remark
(TPnCKS0 to TPnCKS2 bits)
External trigger input
Register initial setting
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register,
TPnCCR0 register
TPnCCR1 register
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
TPnCCR1 register
TPnCTL0 register
TOPn1 pin output
(TIPn0 pin input)
TPnCE bit = 1
16-bit counter
START
n = 0 to 2, 5
m = 0, 1
TPnCE bit
FFFFH
0000H
Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode
<1>
Initial setting of these
registers is performed
before setting the
TPnCE bit to 1.
The TPnCKS0 to
TPnCKS2 bits can be
set at the same time
when counting has been
started (TPnCE bit = 1).
Trigger wait status
D
10
D
D
00
10
D
00
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
<2>
<2> TPnCCR0, TPnCCR1 register setting change flow
<3> Count operation stop flow
Setting of TPnCCR0, TPnCCR1
D
11
D
D
01
11
D
01
TPnCE bit = 0
registers
STOP
<3>
Count operation is
stopped
As rewriting the
TPnCCRm register
immediately forwards
to the CCRm buffer
register, rewriting
immediately after
the generation of the
INTTPnCCR0 signal
is recommended.
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