UPD70F3735GC-GAD-AX Renesas Electronics America, UPD70F3735GC-GAD-AX Datasheet - Page 672

• Manufacturer Part Number: UPD70F3735GC-GAD-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GC-GAD-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
(3) Oscillation stabilization time select register (OSTS)
The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash
memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register.
The OSTS register can be read or written 8-bit units.
Reset sets this register to 06H.
Note The oscillation stabilization time and setup time are required when the STOP mode and
Cautions 1. The wait time following release of the STOP mode does not include the time
Remark
OSTS
After reset: 06H
IDLE2 mode are released, respectively.
OSTS2
2. Be sure to clear bits 3 to 7 to “0”.
3. The oscillation stabilization time following reset release differs depending on
f
X
0
0
0
0
1
1
1
1
0
= Main clock oscillation frequency
until the clock oscillation starts (“a” in the figure below) following release of
the STOP mode, regardless of whether the STOP mode is released by reset
input or the occurrence of an interrupt request signal.
the option byte setting. For details, see CHAPTER 27 OPTION BYTE.
Voltage waveform of X1 pin
R/W
OSTS1
0
0
0
1
1
0
0
1
1
Address: FFFFF6C0H
OSTS0
0
1
0
1
0
1
0
1
0
V
SS
Selection of oscillation stabilization time/setup time
2
2
2
2
2
2
2
Setting prohibited
STOP mode release
10
11
12
13
14
15
16
/f
/f
/f
/f
/f
/f
/f
0
X
X
X
X
X
X
X
a
0
OSTS2
0.256 ms
0.512 ms
1.024 ms
2.048 ms
4.096 ms
8.192 ms
16.38 ms
CHAPTER 21 STANDBY FUNCTION
4 MHz
OSTS1
f
X
13.107 ms
0.205 ms
0.410 ms
0.819 ms
1.638 ms
3.277 ms
6.554 ms
5 MHz
OSTS0
Note
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