SAF-TC1167-128F133HL AD Infineon Technologies, SAF-TC1167-128F133HL AD Datasheet - Page 11

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SAF-TC1167-128F133HL AD

Manufacturer Part Number
SAF-TC1167-128F133HL AD
Description
IC MCU 32BIT FLASH 176-LQFP
Manufacturer
Infineon Technologies
Series
TC116xr

Specifications of SAF-TC1167-128F133HL AD

Core Processor
TriCore
Core Size
32-Bit
Speed
133MHz
Connectivity
ASC, CAN, EBI/EMI, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
88
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 32x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFQFP
Data Bus Width
32 bit
Data Ram Size
104 KB
Interface Type
ASC, MLI, MSC, SSC
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
88
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (12 bit, 16 Channel) / 10 bit, 4 Channel
Packages
PG-LQFP-176
Max Clock Frequency
133.0 MHz
Sram (incl. Cache)
128.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
36
Program Memory
1.0 MB
For Use With
B158-H8690-X-0-7600IN - KIT STARTER TC116X SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
SP000602800
2
This Data Sheet describes the Infineon TC1167, a 32-bit microcontroller DSP, based on
the Infineon TriCore Architecture.
2.1
This document is designed to be read primarily by design engineers and software
engineers who need a detailed description of the interactions of the TC1167 functional
units, registers, instructions, and exceptions.
This TC1167 Data Sheet describes the features of the TC1167 with respect to the
TriCore Architecture. Where the TC1167 directly implements TriCore architectural
functions, this manual simply refers to those functions as features of the TC1167. In all
cases where this manual describes a TC1167 feature without referring to the TriCore
Architecture, this means that the TC1167 is a direct implementation of the TriCore
Architecture.
Where the TC1167 implements a subset of TriCore architectural features, this manual
describes the TC1167 implementation, and then describes how it differs from the TriCore
Architecture. Such differences between the TC1167 and the TriCore Architecture are
documented in the section covering each such subject.
2.1.1
A complete description of the TriCore architecture is found in the document entitled
“TriCore Architecture Manual”. The architecture of the TC1167 is described separately
this way because of the configurable nature of the TriCore specification: Different
versions of the architecture may contain a different mix of systems components. The
TriCore architecture, however, remains constant across all derivative designs in order to
preserve compatibility.
This Data Sheets together with the “TriCore Architecture Manual” are required to
understand the complete TC1167 micro controller functionality.
2.1.2
This document uses the following text conventions for named components of the
TC1167:
Data Sheet
Functional units of the TC1167 are given in plain UPPER CASE. For example: “The
SSC supports full-duplex and half-duplex synchronous communication”.
Pins using negative logic are indicated by an overline. For example: “The external
reset pin, ESR0, has a dual function.”.
Bit
“Module_Register name.Bit field” or “Module_Register name.Bit”. For example: “The
Current CPU Priority Number bit field CPU_ICR.CCPN is cleared”. Most of the
fields
Introduction
About this Document
Related Documentations
Text Conventions
and
bits
in
registers
7
are
in
general
referenced
Introduction
V1.3, 2009-10
TC1167
as

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