SAF-TC1167-128F133HL AD Infineon Technologies, SAF-TC1167-128F133HL AD Datasheet - Page 119

• Manufacturer Part Number: SAF-TC1167-128F133HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC116xr

Specifications of SAF-TC1167-128F133HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 104 KB
• Interface Type: ASC, MLI, MSC, SSC
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel) / 10 bit, 4 Channel
• Packages: PG-LQFP-176
• Max Clock Frequency: 133.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• For Use With: B158-H8690-X-0-7600IN - KIT STARTER TC116X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000602800

Table 22
Parameter
MLI Transmitter Timing
TCLK clock period
TCLK high time
TCLK low time
TCLK rise time
TCLK fall time
TDATA/TVALID output
delay time
TREADY setup time to
TCLK rising edge
TREADY hold time from
TCLK rising edge
MLI Receiver Timing
RCLK clock period
RCLK high time
RCLK low time
RCLK rise time
RCLK fall time
RDATA/RVALID setup
time to RCLK falling edge
RDATA/RVALID hold time
from RCLK rising edge
RREADY output delay time
1)
2) The following formula is valid:
3) The min./max. TCLK low/high times t
4) For high-speed MLI interface, strong driver sharp edge selection (class A2 pad) is recommended for TCLK.
5) The following formula is valid:
6) The min. and max. value of is parameter can be adjusted by considering the other receiver timing parameters.
Data Sheet
T
regarded additionally to t
MLImin.
=
T
SYS
= 1/
MLI Transmitter/Receiver Timing
(Operating Conditions apply), C
f
SYS
. When
11
/t
12
.
f
t
t
SYS
11
21
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
+
+
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
= 80 MHz,
t
t
12
22
11
=
=
CC
/t
t
t
CC 2 ×
CC 0.45 ×
CC –
CC –
CC -3
SR 18
SR 0
SR 1 ×
SR –
SR –
SR –
SR –
SR 4.2
SR 2.2
CC 0
10
12
20
include the PLL jitter of
t
10
Min.
0.45 ×
= 25 ns and
114
T
T
MLI
MLI
L
t
t
10
10
= 50 pF
t
Typ.
–
0.5 ×
0.5 ×
–
–
–
–
–
–
0.5 ×
0.5 ×
–
–
–
–
–
20
Values
= 12.5 ns.
f
t
t
t
t
SYS
10
10
20
20
. Fractional divider settings must be
Max.
–
0.55 ×
0.55 ×
4)
4)
4.4
–
–
–
–
–
4
4
–
–
16
Electrical Parameters
t
t
10
10
Unit Note /
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V1.3, 2009-10
Test Co
ndition
1)
2)3)
2)3)
–
–
–
–
–
1)
5)6)
5)6)
7)
7)
–
–
–
TC1167