SAF-TC1167-128F133HL AD Infineon Technologies, SAF-TC1167-128F133HL AD Datasheet - Page 20

• Manufacturer Part Number: SAF-TC1167-128F133HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC116xr

Specifications of SAF-TC1167-128F133HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 104 KB
• Interface Type: ASC, MLI, MSC, SSC
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel) / 10 bit, 4 Channel
• Packages: PG-LQFP-176
• Max Clock Frequency: 133.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• For Use With: B158-H8690-X-0-7600IN - KIT STARTER TC116X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000602800

2.2.3
The TC1167 includes a high Performance CPUand a Peripheral Control Processor.
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2.2.3.1
This chapter gives an overview about the TriCore 1 architecture.
TriCore (TC1.3.1) Architectural Highlights
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High-efficiency TriCore Instruction Set
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Integrated CPU related On-Chip Memories
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1) Software configurable. Available options are described in the CPU chapter.
Data Sheet
Unified RISC MCU/DSP
32-bit architecture with 4 Gbytes unified data, program, and input/output address
space
Fast automatic context-switching
Multiply-accumulate unit
Floating point unit
Saturating integer arithmetic
High-performance on-chip peripheral bus (FPI Bus)
Register based design with multiple variable register banks
Bit handling
Packed data operations
Zero overhead loop
Precise exceptions
Flexible power management
16/32-bit instructions for reduced code size
Data types include: Boolean, array of bits, character, signed and unsigned integer,
integer with saturation, signed fraction, double-word integers, and IEEE-754 single-
precision floating point
Data formats include: Bit, 8-bit byte, 16-bit half-word, 32-bit word, and 64-bit double-
word data formats
Powerful instruction set
Flexible and efficient addressing mode for high code density
Instruction memory: 24 KB total. After reset, configured into:
– 24 Kbyte Scratch-Pad RAM (SPRAM)
– 0 Kbyte Instruction Cache (ICACHE)
Data memory: 72 KB total. After reset, configured into:
On Chip CPU Core
High-performance 32-bit CPU
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Introduction
V1.3, 2009-10
TC1167