MC68HC705J1ACDW Freescale Semiconductor, MC68HC705J1ACDW Datasheet - Page 104

IC MCU 4MHZ 1.2K OTP 20-SOIC

MC68HC705J1ACDW

Manufacturer Part Number
MC68HC705J1ACDW
Description
IC MCU 4MHZ 1.2K OTP 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705J1ACDW

Core Processor
HC05
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
14
Program Memory Size
1.2KB (1.2K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC705J1ACDWE
Manufacturer:
INTERSIL
Quantity:
1 000
External Interrupt Module (IRQ)
8.3.1 IRQ/V
8.3.2 Optional External Interrupts
Technical Data
PP
Pin
An interrupt signal on the IRQ/V
request. The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If edge- and level-sensitive triggering is selected, a falling edge or a low
level on the IRQ/V
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. An external interrupt request is latched as long as any
source is holding the IRQ/V
If level-sensitive triggering is selected, the IRQ/V
external resistor to V
used, it must be tied to the V
If edge-sensitive-only triggering is selected, a falling edge on the
IRQ/V
interrupt request can be latched only after the voltage level on the
IRQ/V
The IRQ/V
to improve noise immunity. The voltage on this pin can affect the mode
of operation and should not exceed V
The inputs for the lower four bits of port A (PA0–PA3) can be connected
to the IRQ pin input of the CPU if enabled by the PIRQ bit in the mask
option register. This capability allows keyboard scan applications where
the transitions or levels on the I/O pins will behave the same as the
IRQ/V
active state of the IRQ/V
The PA0–PA3 pins are selected as a group to function as IRQ interrupts
and are enabled by the IRQE bit in the IRQ status and control register.
The PA0–PA3 pins can be positive-edge triggered only or positive-edge
and high-level triggered.
Freescale Semiconductor, Inc.
For More Information On This Product,
PP
PP
PP
pin latches an external interrupt request. A subsequent external
pin returns to logic 1 and then falls again to logic 0.
pin except for the inverted phase (logic 1, rising edge). The
PP
External Interrupt Module (IRQ)
Go to: www.freescale.com
pin contains an internal Schmitt trigger as part of its input
PP
DD
pin latches an external interrupt request. Edge- and
for wired-OR operation. If the IRQ/V
PP
PP
pin is a logic 0 (falling edge).
DD
pin low.
supply.
PP
pin latches an external interrupt
DD
.
MC68HC705J1A — Rev. 4.0
PP
input requires an
PP
pin is not

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